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AD9283BRS-50 датащи(PDF) 8 Page - Analog Devices |
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AD9283BRS-50 датащи(HTML) 8 Page - Analog Devices |
8 / 12 page AD9283 –8– REV. C CODE 2.0 –0.5 –1.0 –1.5 –2.0 0.5 0.0 1.0 1.5 TPC 13. Integral Nonlinearity APPLICATIONS Theory of Operation The analog signal is applied differentially or single-endedly to the inputs of the AD9283. The signal is buffered and fed for- ward to an on-chip sample-and-hold circuit. The ADC core architecture is a bit-per-stage pipeline type converter utilizing switch capacitor techniques. The bit-per-stage blocks determine the 5 MSBs and drive a FLASH converter to encode the 3 LSBs. Each of the 5 MSB stages provides sufficient overlap and error correction to allow optimization of performance with respect to comparator accuracy. The output staging block aligns the data, carries out the error correction and feeds the data to the eight output buffers. The AD9283 includes an on-chip reference (nominally 1.25 V) and generates all clocking signals from one externally applied encode command. This makes the ADC easy to interface with and requires very few external components for operation. ENCODE Input The ENCODE input is fully TTL/CMOS compatible with a nominal threshold of 1.5 V. Care was taken on the chip to match clock line delays and maintain sharp clock logic transi- tions. Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. This ADC uses an on-chip sample-and-hold circuit which is essen- tially a mixer. Any timing jitter on the ENCODE will be com- bined with the desired signal and degrade the high frequency performance of the ADC. The user is advised to give commen- surate thought to the clock source. Analog Input The analog input to the ADC is fully differential and both inputs are internally biased. This allows the most flexible use of ac or dc and differential or single-ended input modes. For peak performance the inputs are biased at 0.3 × VD. See the specification table for allowable common-mode range when dc coupling the input. The inputs are also buffered to reduce the load the user needs to drive. For best dynamic performance, the impedances at AIN and AIN should be matched. The importance of this increases with sampling rate and analog input frequency. The nominal input range is 1.024 V p-p. Digital Outputs The digital outputs are TTL/CMOS compatible. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing to ease interfacing with 2.5 V or 3.3 V logic. The AD9283 goes into a low power state within two clock cycles following the assertion of the PWRDWN input. PWRDWN is asserted with a logic high. During power-down the outputs transition to a high impedance state. The time it takes to achieve optimal performance after disabling the power- down mode is approximately 15 clock cycles. Care should be taken when loading the digital outputs of any high speed ADC. Large output loads create current transients on the chip that can degrade the converter’s performance. Voltage Reference A stable and accurate 1.25 V voltage reference is built into the AD9283 (VREF OUT). In normal operation, the internal refer- ence is used by strapping Pins 2 and 3 of the AD9283 together. The input range can be adjusted by varying the reference volt- age applied to the AD9283. No degradation in performance occurs when the reference is adjusted ±5%. The full-scale range of the ADC tracks reference voltage changes linearly. Whether used or not, the internal reference (Pin 2) should be bypassed with a 0.1 µF capacitor to ground. Timing The AD9283 provides latched data outputs with four pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (Figure 1. Timing Diagram). The minimum guaranteed conversion rate to the ADC is 1 MSPS. The dynamic performance of the converter will degrade at encode rates below this sample rate. Evaluation Board The AD9283 evaluation board offers an easy way to test the AD9283. It only requires a 3 V supply, an analog input and encode clock to test the AD9283. The board is shipped with the 100 MSPS grade ADC. The analog input to the board accepts a 1 V p-p signal centered at ground. J1 should be used (Jump E3–E4, E18–E19) to drive the ADC through Transformer T1. J2 should be used for single- ended input drive (Jump E19–E21). Both J1 and J2 are terminated to 50 Ω on the PCB. Each analog path is ac-coupled to an on-chip resistor divider which provides the required dc bias. A (TTL/CMOS Level) sample clock is applied to connector J3 which is terminated through 50 Ω on the PCB. This clock is buffered by U5 which also provides the clocks for the 574 latches, DAC, and the off-card latch clock CLKCON. (Timing can be modified at E17.) There is a reconstruction DAC (AD9760) on the PCB. The DAC is on the board to assist in debug only—the outputs should not be used to measure performance of the ADC. |
Аналогичный номер детали - AD9283BRS-50 |
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Аналогичное описание - AD9283BRS-50 |
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