AD7734

Data Sheet

Rev. A | Page 6 of 32

TIMING SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Master Clock Range

1

6.144

MHz

t

1

50

ns

SYNC Pulsewidth

t

2

500

ns

RESET Pulsewidth

Read Operation

t

4

0

ns

CS Falling Edge to SCLK Falling Edge Setup Time

t

5

2

SCLK Falling Edge to Data Valid Delay

0

60

ns

DV

0

80

ns

DV

t

5A

2, 3

CS Falling Edge to Data Valid Delay

0

60

ns

DV

0

80

ns

DV

t

6

50

ns

SCLK High Pulsewidth

t

7

50

ns

SCLK Low Pulsewidth

t

8

0

ns

CS Rising Edge after SCLK Rising Edge Hold Time

t

9

4

10

80

ns

Bus Relinquish Time after SCLK Rising Edge

Write Operation

t

11

0

ns

CS Falling Edge to SCLK Falling Edge Setup

t

12

30

ns

Data Valid to SCLK Rising Edge Setup Time

t

13

25

ns

Data Valid after SCLK Rising Edge Hold Time

t

14

50

ns

SCLK High Pulsewidth

t

15

50

ns

SCLK Low Pulsewidth

t

16

0

ns

CS Rising Edge after SCLK Rising Edge Hold Time

1.6 V. See Figure 2 and Figure 3.

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.