V

CC

V

POR

V

PORF

Time

POR

Time

V

CC

Time

V

CC_GH

V

CC_GW

TCA6418E

www.ti.com

SCPS243 – SEPTEMBER 2012

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width

device impedance are factors that affect power-on reset performance. Figure 3 and Table 2 provide more

information on how to measure these specifications.

Figure 3. Glitch Width and Glitch Height

For proper operation of the power-on reset feature, use as directed in the figures and table above.

Interrupt Output

INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or

data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge

(ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the

ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse.

Each change of the I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the

state of the pin does not match the contents of the input port register.

For more information on the interrupt output feature, see Control Register and Command Byte and Typical

Applications.

Copyright © 2012, Texas Instruments Incorporated

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