SDA

SCL

DataLine

Change

SDA

SCL

S

P

StartCondition

StopCondition

TCA6418E

SCPS243 – SEPTEMBER 2012

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connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

the SDA input/output, while the SCL input is high (see Figure 5). After the Start condition, the device address

byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must

not be changed between the Start and the Stop conditions.

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 6).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 5).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 7). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

Figure 5. Definition of Start and Stop Conditions

Figure 6. Bit Transfer

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