TPS40490

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SLVSCB4 – OCTOBER 2013

PIN FUNCTIONS

NAME

I/O

PIN

DESCRIPTION

VOUT

I

1

Output voltage for the controller

AGND

GND

2

Analog signal ground. This pin must be electrically connected to power ground PGND externally.

Reference pin. A ceramic capacitor with a value between 1 nF and 100 nF must be connected between

VREF

O

3

this pin and the AGND pin and placed closely to this pin. This provides an RC filter with 25-k

Ω resistor

inside the die.

NUC

-

4

Pin not used. Connect to ground during normal operation.

NUD

-

5

Pin not used. Connect to ground during normal operation.

SYNC

I

6

External synchronization pin.

I

7

Dead time set bit 1. Connect to 3V3 for 1, leave open for 0.

PGND

8

Power ground. This pin must externally connect to the AGND at a single point.

Low side gate driver turn-off output. Connect the gate of the low side transistor with a short, low

O

9

inductance path.

Low side gate driver turn-on output. Connect the gate of the low side transistor with a short, low

O

10

inductance path.

SW

O

11

This pin must connect to the switching node of the synchronous buck converter.

High side gate driver turn-off output. Connect the gate of the high side transistor with a short, low

O

12

inductance path.

High side gate driver turn-on output. Connect the gate of the high side transistor with a short, low

O

13

inductance path.

Boot capacitor node for high-side FET gate driver supply. The boot capacitor is connected from this pin to

BOOT

O

14

SW.

I

15

Dead time set bit 3. Connect to ground for 0, leave open for 1.

I

16

Dead time set bit 2. Connect to ground for 0, leave open for 1.

Power good indicator. This pin is an open-drain output pin and a 10-k

Ω pull-up resistor is recommended

PGOOD

O

17

to be connected between this pin and V3V.

A resistor from this pin to AGND sets the current limit. This pin provides source current used for over

ILIM

I

18

current protection threshold setting.

A resistor from this pin to AGND sets the oscillator frequency. Even if operating with an external

RT

I

19

synchronization clock, it is required to have a resistor at this pin to set the free running switching

frequency.

This pin must be high for the device to be enabled. If this pin is pulled low, the device is put in a low-

EN

I

20

power consumption shutdown mode. Care must be taken to make sure the voltage at this pin does not

exceed 3.6 V.

Undervoltage lockout. A resistor divider on this pin from VIN to AGND can be used to set the UVLO

UVLO

I

21

threshold.

Input voltage for the controller which is also the input voltage for the DC/DC converter. A 1-µF to 10-µF

I

22

capacitor from this pin to AGND must be added and placed closed to VIN.

Regulated output for gate driver. A ceramic capacitor with a value between 1 µF and 10 µF must be

O

23

connected from this pin to PGND.

Optional External supply to gate driver. A ceramic capacitor with a value between 1 µF and 10 µF must

I

24

be connected from this pin to PGND. A supply of 5 V to 12 V can be connected to this input providing

drive voltage for better efficiency.

3.3-V regulated output. A ceramic by-pass capacitor of 1 µF must be connected between this pin and the

V3V

O

25

AGND pin and placed closely to this pin.

Output of the internal error amplifier. The feedback loop compensation network is connected from this pin

COMP

O

26

to the FB pin.

Negative input to the error amplifier. The output voltage is fed back to this pin through a resistor divider

FB

I

27

network.

SS

I

28

A capacitor must be connected at this pin to AGND. The capacitor value sets the soft-start time.

PAD

Power pad. Must be connected to PCB ground.

Copyright © 2013, Texas Instruments Incorporated

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