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AD7739BRUZ датащи(PDF) 5 Page - Analog Devices |
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AD7739BRUZ датащи(HTML) 5 Page - Analog Devices |
5 / 32 page Data Sheet AD7739 Rev. A | Page 5 of 32 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS AVDD to AGND Voltage 4.75 5.25 V DVDD to DGND Voltage 4.75 5.25 V 2.70 3.60 V AVDD Current (Normal Mode) 13.6 16 mA AVDD Current (Reduced Power Mode) 9.2 11 mA MCLK = 4 MHz AVDD Current (Internal Buffer Off ) 8.5 mA DVDD Current (Normal Mode)13 2.7 3 mA DVDD = 5 V DVDD Current (Normal Mode)13 1.0 1.5 mA DVDD = 3 V Power Dissipation (Normal Mode)13 85 100 mW Power Dissipation (Reduced Power Mode)13 60 70 mW DVDD = 5 V, MCLK = 4 MHz Power Dissipation (Reduced Power Mode)13 50 mW DVDD = 3 V, MCLK = 4 MHz AVDD + DVDD Current (Standby Mode)14 80 μA Power Dissipation (Standby Mode)14 500 μW 1 Specification is not production tested, but is supported by characterization data at initial product release. 2 See Typical Performance Characteristics. 3 Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 4 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 5 Specifications before calibration. ADC zero-scale self-calibration or channel zero-scale system calibration reduce this error to the order of the noise. 6 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the clamp bit in the mode register. See the register and circuit descriptions for details. 7 For specified performance. If the analog input absolute voltage (referred to AGND) changes more than 0.5 V during one conversion time, the result can be affected by distortion in the input buffer. This limit does not apply to analog input absolute voltages below 3 V. 8 If chopping is enabled or when switching between channels, a dynamic current charges the capacitance of the multiplexer. See the circuit description for details. 9 For specified performance. Part is functional with lower VREF. 10 Dynamic current charging the sigma-delta (Σ-Δ) modulator input switching capacitor. 11 Outside the specified calibration range, calibration is possible but the performance may degrade. 12 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 13 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register). 14 External MCLKIN = 0 V or DVDD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD. TIMING SPECIFICATIONS AVDD = 5 V ± 5%, DVDD = 2.7 V to 3.6 V or 5 V ± 5%, Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.1 Table 2. Parameter Min Typ Max Unit Test Conditions/Comments MASTER CLOCK RANGE 1 6.144 MHz 1 4 MHz Reduced power mode t1 50 ns SYNC pulse width t2 500 ns RESET pulse width READ OPERATION t4 0 ns CS falling edge to SCLK falling edge setup time t52 SCLK falling edge to data valid delay 0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DVDD of 2.7 V to 3.3 V t5A2, 3 CS falling edge to data valid delay 0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DVDD of 2.7 V to 3.3 V t6 50 ns SCLK high pulse width t7 50 ns SCLK low pulse width t8 0 ns CS rising edge after SCLK rising edge hold time t94 10 80 ns Bus relinquish time after SCLK rising edge |
Аналогичный номер детали - AD7739BRUZ |
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Аналогичное описание - AD7739BRUZ |
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