AD7739

Data Sheet

Rev. A | Page 6 of 32

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

WRITE OPERATION

0

ns

CS falling edge to SCLK falling edge setup

30

ns

Data valid to SCLK rising edge setup time

25

ns

Data valid after SCLK rising edge hold time

50

ns

SCLK high pulse width

50

ns

SCLK low pulse width

0

ns

CS rising edge after SCLK rising edge hold time

1.6 V. See Figure 2 and Figure 3.

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Specifications are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

TIMING DIAGRAMS

Figure 2. Read Cycle Timing Diagram

Figure 3. Write Cycle Timing Diagram

Figure 4. Load Circuit for Access Time and Bus Relinquish Time

DOUT

MSB

LSB

CS

SCLK

03742-0-002

DIN

MSB

LSB

SCLK

CS

03742-0-003

100

A AT DV

100

A AT DV

1.6V

TO OUTPUT

PIN

50pF

03742-0-004