ADC1175-50

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SNAS027G – JANUARY 2000 – REVISED APRIL 2013

SPECIFICATION DEFINITIONS

ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

signal is the full power bandwidth.

delay.

BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to

first code transition input voltage. Note that this is different from the normal Zero Scale Error.

DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency

reconstructed sine wave at two different d.c. levels.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB. DNL is measured at the rated clock frequency with a ramp input.

DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave

at two different d.c. levels.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio, or SINAD. ENOB is defined as (SINAD

− 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual codes from a line drawn from

zero scale (1/2 LSB below the first code transition) through positive full scale (1/2 LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

The end point test method is used. INL is measured at rated clock frequency with a ramp input.

OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the

output pins.

OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data

is presented to the output stage. Data for any given sample is available the Pipeline Delay plus the Output Delay

after that sample is taken. New data is available at every clock cycle, but the data lags the conversion by the

pipeline delay.

switch to open (in other words, for the Sample/Hold circuit to go from the “sample” mode into the “hold” mode).

clock goes low.

SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value of the input signal to the rms value of the other

spectral components below one-half the sampling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio of the rms value of the input signal to

the rms value of all of the other spectral components below half the clock frequency, including harmonics but

excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum

that is not present at the input.

TOP OFFSET is the difference between the positive reference voltage and the input voltage that just causes the

input voltage. Note that this is different from the normal Full Scale Error.

TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first six harmonic components to the

rms value of the input signal.

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