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TLC32046C датащи(PDF) 3 Page - Texas Instruments

номер детали TLC32046C
подробное описание детали  Wide-Band Analog Interface Circuit
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TLC32046C датащи(HTML) 3 Page - Texas Instruments

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Contents
Section
Title
Page
1
Introduction
1–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features
1–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Functional Block Diagrams
1–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Terminal Assignments
1–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Ordering Information
1–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Terminal Functions
1–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Detailed Description
2–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Internal Timing Configuration
2–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Analog Input
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
A/D Band-Pass Filter, Clocking, and Conversion Timing
2–4
. . . . . . . . . . . . . . . . . . . .
2.4
A/D Converter
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Analog Output
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
D/A Low-Pass Filter, Clocking, and Conversion Timing
2–4
. . . . . . . . . . . . . . . . . . . . .
2.7
D/A Converter
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8
Serial Port
2–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9
Synchronous Operation
2–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.1
One 16-Bit Word
2–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.2
Two 8-Bit Bytes
2–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.3
Synchronous Operating Frequencies
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Asynchronous Operation
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.1 One 16-Bit Word
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.2 Two 8-Bit Bytes
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.3 Asynchronous Operating Frequencies
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Operation of TLC32046C and TLC32046I With Internal Voltage Reference
2–7
. . .
2.12 Operation of TLC32046C AND TLC32046I With External Voltage Reference
2–7
.
2.13 Reset
2–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 Loopback
2–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15 Communications Word Sequence
2–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.1 Primary DR Word Bit Pattern
2–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.2 Primary DX Word Bit Pattern
2–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.3 Secondary DX Word Bit Pattern
2–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16 Reset Function
2–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.17 Power-Up Sequence
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.18 AIC Register Constraints
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19 AIC Responses to Improper Conditions
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.20 Operation With Conversion Times Too Close Together
2–12
. . . . . . . . . . . . . . . . . . . . .
2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs – Asynchronous Operation
2–12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.22 More Than One Transmit Frame Sync Occurring Between Two Receive
Frame Syncs – Asynchronous Operation
2–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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