74HC_HCT595_Q100

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 2 — 10 April 2013

4 of 23

NXP Semiconductors

74HC595-Q100; 74HCT595-Q100

8-bit serial-in, serial or parallel-out shift register with output latches;

3-state

6.

Pinning information

6.1 Pinning

Fig 5.

Pin configuration SO16

Fig 6.

Pin configuration (T)SSOP16

+&4

+&74

44

4'6

42(

4

67&3

4

6+&3

405

*1'

46

DDD

































+&4

+&74

44

4'6

42(

4

67&3

4

6+&3

405

*1'

46

DDD

































(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or

mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to

GND.

Fig 7.

Pin configuration for DHVQFN16

DDD

+&4

+&74

4

05

4

6+&3

4

67&3

4

2(

4

'6

4

4

7UDQVSDUHQWWRS YLHZ

























WHUPLQDO

LQGH[DUHD