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CAT28F020HRI-90T датащи(PDF) 9 Page - ON Semiconductor

номер детали CAT28F020HRI-90T
подробное описание детали  2 Megabit CMOS Flash Memory
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производитель  ONSEMI [ON Semiconductor]
домашняя страница  http://www.onsemi.com
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CAT28F020HRI-90T датащи(HTML) 9 Page - ON Semiconductor

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CAT28F020
9
Doc. No. MD-1029, Rev. F
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
Figure 4. A.C. Timing for Erase Operation
28F020 F11
ADDRESSES
CE (E)
OE (G)
WE (W)
DATA (I/O)
VCC
VPP
tWC
tWC
tRC
tCS
tCH
tCS
tCH
tCH
tEHQZ
tDF
tGHWL
tWPH
tWHWH2
tWHGL
tWP
tDS
HIGH-Z
DATA IN
= 20H
DATA IN
= A0H
VALID
DATA OUT
tDH
tWP
tDH
tDS
tDS
tWP
tDH
tOLZ
tOE
tOH
tLZ
tCE
tVPEL
VPPH
VPPL
0V
5.0V
VCC POWER-UP
& STANDBY
SETUP ERASE
COMMAND
ERASE
COMMAND
ERASING
ERASE VERIFY
COMMAND
ERASE
VERIFICATION
VCC POWER-DOWN/
STANDBY
tAS
tAH
DATA IN
= 20H
tWC
WRITE OPERATIONS
The following operations are initiated by observing the
sequence specified in the Write Command Table.
Read Mode
The device can be put into a standard READ mode by
initiating a write cycle with 00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or E2PROM Read.
Signature Mode
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code 90H into the command register while keeping
VPP high. A read cycle from address 0000H with CE and
OE low (and WE high) will output the device signature.
CATALYST Code = 00110001 (31H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
28F020 Code = 1011 1101 (BDH)
Erase Mode
During the first Write cycle, the command 20H is written
into the command register. In order to commence the
erase operation, the identical command of 20H has to be
written again into the register. This two-step process
ensures against accidental erasure of the memory con-
tents. The final erase cycle will be stopped at the rising
edge of WE, at which time the Erase Verify command
(A0H) is sent to the command register. During this cycle,
the address to be verified is sent to the address bus and
latched when WE goes low. An integrated stop timer
allows for automatic timing control over this operation,
eliminating the need for a maximum erase timing speci-
fication. Refer to AC Characteristics (Program/Erase)
for specific timing parameters.


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