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DAC725JP датащи(PDF) 3 Page - Burr-Brown (TI) |
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DAC725JP датащи(HTML) 3 Page - Burr-Brown (TI) |
3 / 7 page 3 ® DAC725 ABSOLUTE MAXIMUM RATINGS VDD to COMMON ........................................................................ 0V, +15V +VCC to COMMON ...................................................................... 0V, +18V –VCC to COMMON ...................................................................... 0V, –18V Digital Data Inputs to COMMON ...................................... –0.5V, VDD + 0.5 DC Current any Input ...................................................................... ±10mA Reference Out to COMMON ........................ Indefinite Short to COMMON VOUT ............................................................ Indefinite Short to COMMON External Voltage Applied to RF ......................................................... ±18V External Voltage Applied to D/A Output ............................................... ±5V Power Dissipation ........................................................................ 2000mW Storage Temperature ...................................................... –60 °C to +150°C Lead Temperature (soldering, 10s) .................................................. 300 °C NOTE: These devices are sensitive to electrostatic discharge. Appropriate I.C. handling procedures should be followed. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum condi- tions for extended periods may affect device reliability. CONNECTION DIAGRAM High Byte Latch Low Byte Latch D/A Latch 8 8 16 16- Bit D/A GA (A) SJ (A) V WR (A) CS (A) –V +V CS (B) WR (B) GA (B) SJ (B) V CLR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DD 2 0 1 ACOM (A) CC CC ACOM (B) OUT V A A A 15 14 13 12 11 10 ) ) ) ) ) ) ) ) (D (D (D (D (D (D 7 6 5 4 3 2 D D D D D D 9 8 (D (D 1 0 D D DCOM High Byte Latch Low Byte Latch D/A Latch 8 8 16 16- Bit D/A OUT (A) (B) PIN DESIGNATOR DESCRIPTION 1 CLR Clear line. Sets the D/A register to 0000HEX, which gives bipolar zero on the D/A output. 2VDD Logic supply (+5V). 3A2 Latch enable for D/A latch (active low). 4A0 Latch enable for “low byte” input (active low). 5A1 Latch enable for “high byte” input (active low). 6D7 (D15) Input for data bit 7 if en- (MSB) abling low byte (LB) latch, or data bit 15 if enabling the high byte (HB) latch. 7D6 (D14) Input for data bit 6 if en- abling LB latch, or data bit 14 if enabling HB latch. 8D5 (D13) Data bit 5 (LB) or data bit 13 (HB). 9D4 (D12) Data bit 4 (LB) or data bit 12 (HB). 10 D3 (D11) Data bit 3 (LB) or data bit 11 (HB). 11 D2 (D10) Data bit 2 (LB) or data bit 10 (HB). 12 D1 (D9) Data bit 1 (LB) or data bit 9 (HB). 13 D0 (D8) Data bit 0 (LB) or data bit 8 (HB). 14 DCOM Digital common. 15 VOUT (B) Voltage output for DAC B. 16 ACOM (B) Analog common for DAC B. 17 SJ (B) Summing junction of the in- ternal op amp for DAC B. 18 GA (B) Gain adjust pin for DAC B. 19 WR (B) Write control line for DAC B. 20 CS (B) Chip select control line for DAC B. 21 +VCC Positive supply voltage (+15V). 22 –VCC Negative supply voltage (–15V). 23 CS (A) Chip select control line for DAC A. 24 WR (A) Write control line for DAC A. 25 VOUT (A) Voltage output for DAC A. 26 ACOM (A) Analog common for DAC A. 27 SJ (A) Summing junction of the in- ternal op amp for DAC A. 28 GA (A) Gain adjust pin for DAC A. PIN DESCRIPTIONS ORDERING INFORMATION LINEARITY ERROR TEMPERATURE MODEL max (% of FSR) RANGE DAC725JP ±0.012 0 °C to +70°C DAC725KP ±0.006 0 °C to +70°C PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER(1) DAC725JP 28-Pin Plastic DIP 215 DAC725KP 28-Pin Plastic DIP 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. |
Аналогичный номер детали - DAC725JP |
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Аналогичное описание - DAC725JP |
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