3

®

DAC811

MINIMUM

RELATIVE

DIFFERENTIAL

PACKAGE

SPECIFICATION

ACCURACY

LINEARITY

DRAWING

TEMPERATURE

ORDERING

TRANSPORT

PRODUCT

(LSB)

(LSB)

PACKAGE

NUMBER

RANGE

MEDIA

DAC811AH

±1/2 LSB

3/4

CerDIP-28

149

–25

°C to +85°C

DAC811AH

Rails

DAC811JP

±1/2 LSB

3/4

DIP-28

215

0

°C to +70°C

DAC811JP

Rails

DAC811JU

±1/2 LSB

3/4

SOIC-28

217

0

°C to +70°C

DAC811JU

Rails

""

"

"

"

"

DAC811JU/1K

Tape and Reel

DAC811KP

±1/4 LSB

1/2

DIP-28

215

0

°C to +70°C

DAC811KP

Rails

DAC811KU

±1/4 LSB

1/2

SOIC-28

217

0

°C to +70°C

DAC811KU

Rails

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces

of “DAC811JU/1K” will get a single 1000-piece Tape and Reel.

ACOM to DCOM ..................................................................................

±7V

Digital Inputs (Pins 2–14, 16–19) to DCOM ...................... –0.4V to +18V

External Voltage Applied to 10V Range Resistor ............................

±12V

Ref Out ............................................................. Indefinite Short to ACOM

External Voltage Applied to DAC Output ................................ –5V to +5V

Power Dissipation ........................................................................ 1000mW

Lead Temperature (soldering, 10s) ............................................... +300

°C

Max Junction Temperature ............................................................ +165

°C

Thermal Resistance,

θ

Ceramic DIP .................................................................................. 65

°C/W

NOTE: Stresses above those listed above may cause permanent damage to

the device. Exposure to absolute maximum conditions for extended periods

may affect device reliability.

PIN

NAME

FUNCTION

Logic supply, +5V.

2

WR

Write, command signal to load latches. Logic low

loads latches.

3

LDAC

Load D/A converter, enables WR to load the D/A

latch. Logic low enables.

Nibble A, enables WR to load input latch A (the

most significant nibble). Logic low enables.

Nibble B, enables WR to load input latch B. Logic

low enables.

Nibble C, enables WR to load input latch C (the

least significant nibble). Logic low enables.

Data bit 12, MSB, positive true.

Data bit 11.

Data bit 10.

10

Data bit 9.

11

Data bit 8.

12

Data bit 7.

13

Data bit 6.

14

Data bit 5.

15

DCOM

16

Data bit 1, LSB.

17

Data bit 2.

18

Data bit 3.

19

Data bit 4.

20

Analog supply input, +15V or +12V.

21

Analog supply input, –15V or –12V.

22

Gain Adj

To externally adjust gain.

23

ACOM

Analog common,

±V

24

D/A converter voltage output.

25

10V Range

Connect to pin 24 for 10V range.

26

SJ

Summing junction of output amplifier.

27

BPO

Bipolar offset. Connect to pin 26 for bipolar

operation.

28

Ref Out

6.3V reference output.

PIN DESCRIPTIONS

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE/ORDERING INFORMATION

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.