поискавой системы для электроныых деталей |
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SN74LS256D датащи(PDF) 4 Page - Motorola, Inc |
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SN74LS256D датащи(HTML) 4 Page - Motorola, Inc |
4 / 6 page 5-424 FAST AND LS TTL DATA SN54/74LS256 AC SET-UP REQUIREMENTS (TA = 25°C) Symbol Parameter Limits Unit Test Conditions Symbol Parameter Min Typ Max Unit Test Conditions ts Data Setup Time 20 ns Figures 4 & 6 VCC = 5.0 V ts Address Setup Time 0 ns Figures 4 & 6 VCC = 5.0 V th Data Hold Time 0 ns Figure 4 VCC = 5.0 V th Address Hold Time 15 ns Figure 6 CC = 5.0 V tW Enable Pulse Width 15 ns Figure 1 ts Figure 1. Turn-on and Turn-off Delays, Enable To Output and Enable Pulse Width Figure 4. Setup and Hold Time, Data to Enable Figure 2. Turn-on and Turn-off Delays, Data to Output Figure 3. Turn-on and Turn-off Delays, Address to Output Figure 5. Turn-on Delay, Clear to Output Figure 6. Setup Time, Address to Enable (See Notes 1 and 2) NOTES: 1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 2. The shaded areas indicate when the inputs are permitted to change for predictable output performance. OTHER CONDITIONS: CL = H, A = STABLE OTHER CONDITIONS: E = L, CL = H, A = STABLE OTHER CONDITIONS: E = L, CL = L, D = H OTHER CONDITIONS: C = H, A = STABLE OTHER CONDITIONS: E = H 1.3 V tPHL tPLH 1.3 V D E Q 1.3 V 1.3 V 1.3 V 1.3 V tPLH tPHL D Q 1.3 V 1.3 V tPHL C Q 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V A1 A1 Q1 tPLH D E Q th(H) th(L) 1.3 V OTHER CONDITIONS: CL = H STABLE ADDRESS A E 1.3 V 1.3 V ts(H) ts(L) tPHL th tpw tpw Q=D Q=D AC WAVEFORMS |
Аналогичный номер детали - SN74LS256D |
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Аналогичное описание - SN74LS256D |
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