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DAC3151IRGCT датащи(PDF) 7 Page - Texas Instruments

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номер детали DAC3151IRGCT
подробное описание детали  Single 14-/12-/10-Bit 500 MSPS Digital-to-Analog Converters
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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DAC3151IRGCT датащи(HTML) 7 Page - Texas Instruments

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DAC3151
DAC3161
DAC3171
www.ti.com
SLAS959A – AUGUST 2013 – REVISED AUGUST 2013
PIN ASSIGNMENT TABLE – DAC3151 (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
DATA INTERFACE
DATA[9:0]P/N
9/10-
I
LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100
Ω
19/20
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two data
transfers per DATACKP/N clock cycle.
22/23
26/27,
The data format is interleaved with channel A (rising edge) and channel B falling edge.
29/30,
In the default mode (reverse bus not enabled):
31/32
DATA13P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
DATACLKP/N
24/25
I
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in
multiplexed output mode.
SYNCP/N
6/7
I
Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge
of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
ALIGNP/N
4/5
I
LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can
be left unconnected.
OUTPUT/CLOCK
DACCLKP/N
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
IOUTAP/N
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input
results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
REFERENCE
EXTIO
58
I/O
Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
57
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960
Ω resistor to GND.
POWER SUPPLY
IOVDD
45
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
CLKVDD18
3
I
1.8V clock supply
DIGVDD18
21, 28
I
1.8V digital supply. Also supplies LVDS receivers.
VDDA18
50, 64
I
Analog 1.8V supply
VDDA33
55, 56,
I
Analog 3.3V supply
59
VFUSE
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
NC
33/34-
Not Used. These pins can be left open or tied to GROUND in actual application use. It is recommended
39/40,
to turn off pin 33-40 (register lvdsdata_ena) to save power.
51, 52,
53, 54
62, 63
Copyright © 2013, Texas Instruments Incorporated
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