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CAT24C02CWA-1.8 датащи(PDF) 4 Page - Catalyst Semiconductor |
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CAT24C02CWA-1.8 датащи(HTML) 4 Page - Catalyst Semiconductor |
4 / 9 page CAT24C02C 4 Doc. No. 25086-00 8/99 S-1 FUNCTIONAL DESCRIPTION The CAT24C02C supports the I2C Bus data transmis- sion protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a re- ceiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24C02C operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. PIN DESCRIPTIONS SCL: Serial Clock The CAT24C02C serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT24C02C bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. I2C BUS PROTOCOL The following defines the features of the I2C bus proto- col: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. Figure 2. Write Cycle Timing Figure 1. Bus Timing Figure 3. Start/Stop Timing 5020 FHD F05 5020 FHD F04 5020 FHD F03 tHIGH SCL SDA IN SDA OUT tLOW tF tLOW tR tBUF tSU:STO tSU:DAT tHD:DAT tHD:STA tSU:STA tAA tDH tWR STOP CONDITION START CONDITION ADDRESS ACK 8TH BIT BYTE n SCL SDA START BIT SDA STOP BIT SCL |
Аналогичный номер детали - CAT24C02CWA-1.8 |
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Аналогичное описание - CAT24C02CWA-1.8 |
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