поискавой системы для электроныых деталей |
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CAT25C17S16I-TE13 датащи(PDF) 9 Page - Catalyst Semiconductor |
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CAT25C17S16I-TE13 датащи(HTML) 9 Page - Catalyst Semiconductor |
9 / 10 page 9 CAT25C03/05/09/17/33 Doc. No. 25068-00 2/98 Advanced Figure 9. HOLD HOLD HOLD HOLD HOLD Timing DESIGN CONSIDERATIONS The CAT25C03/05/09/17/33 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25C03/05/09/17/33 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle Figure 8. Page Write Instruction Timing SK SI CS SO 0 0 0 0 0 0 1 0 ADDRESS Data Byte 1 012345678 21 22 23 24-31 32-39 Data Byte 2 Data Byte 3 Data Byte N is ignored and programming is continued. On power up, SO is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT25C03/05/ 09/17/33, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. 25C128 F10 CS SCK HOLD SO tCD tHD tHD tCD tLZ tHZ |
Аналогичный номер детали - CAT25C17S16I-TE13 |
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Аналогичное описание - CAT25C17S16I-TE13 |
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