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CAT28F001T-90TT датащи(PDF) 11 Page - Catalyst Semiconductor |
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CAT28F001T-90TT датащи(HTML) 11 Page - Catalyst Semiconductor |
11 / 18 page CAT28F001 11 Doc. No. 25071-00 2/98 F-1 Bus Operation Command Comments Write Program Data = 40H Setup Address = Bytes to be Programmed Write Program Data to be programmed Address = Byte to be Programmed Read Status Register Data. Toggle OE or CE to update Status Register Check SR.7 Standby 1 = Ready, 0 = Busy Repeat for subsequent bytes. Full Status check can be done after each byte or after a sequence of bytes. Write FFH after the last byte programming operation to reset the device to Read Array Mode. Bus Operation Command Comments Standby Check SR.3 1 = VPP Low Detect Standby Check SR.3 1 = Byte Program Error SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.3 is only cleared by the Clear Status Register Command, in case where multiple bytes are programmed before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. START WRITE 40H, BYTE ADDRESS READ STATUS REGISTER SR.7 = 1? FULL STATUS CHECK IF DESIRED BYTE PROGRAM COMPLETED STATUS REGISTER DATA READ (SEE ABOVE) SR.3 = 0? SR.4 = 0? BYTE PROGRAM SUCCESSFUL NO NO WRITE BYTE ADDRESS/DATA FULL STATUS CHECK PROCEDURE NO VPP RANGE ERROR BYTE PROGRAM ERROR YES YES YES Figure 4 Byte Programming Flowchart IN-SYSTEM OPERATION For on-board programming, the RP pin is the most convenient means of altering the boot block. Before issuing Program or Erase confirms commands, RP must transition to VHH. Hold RP at this high voltage throughout the program or erase interval (until after Status Register confirm of successful completion). At this time, it can return to VIH or VIL. |
Аналогичный номер детали - CAT28F001T-90TT |
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Аналогичное описание - CAT28F001T-90TT |
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