UC3842B, 43B UC2842B, 43B

11

MOTOROLA ANALOG IC DEVICE DATA

Figure 20. External Clock Synchronization

Figure 21. External Duty Cycle Clamp and

Multi–Unit Synchronization

Figure 22. Adjustable Reduction of Clamp Level

Figure 23. Soft–Start Circuit

2(3)

EA

Bias

+

Osc

R

R

R

2R

5(9)

1(1)

4(7)

8(14)

RT

CT

Vref

0.01

The diode clamp is required if the Sync amplitude is large enough to cause the bottom

side of CT to go more than 300 mV below ground.

External

Sync

Input

47

+

R

R

R

2R

Bias

Osc

EA

5(9)

1(1)

2(3)

4(7)

8(14)

To Additional

UCX84XBs

R

S

Q

8

4

6

5

2

1

C

3

7

RA

RB

5.0k

5.0k

5.0k

MC1455

f

+

1.44

(RA ) 2RB)C

D(max) +

RB

RA ) 2RB

+

–

5.0V Ref

+

–

S

R

Q

Bias

+

Osc

R

R

R

2R

EA

1.0V

5(9)

7(11)

6(10)

5(8)

3(5)

RS

Q1

VCC

Vin

1(1)

2(3)

4(7)

8(14)

R1

VClamp

R2

5.0V Ref

+

–

S

R

Q

Bias

+

1.0mA

Osc

R

R

R

2R

EA

1.0V

5(9)

1(1)

2(3)

4(7)

8(14)

C

1.0M

tSoft–Start ≈ 3600C in µF

7(12)

Comp/Latch

1.0 mA

Ipk(max) [

VClamp

RS

Where: 0

≤ VClamp ≤ 1.0 V

VClamp ≈

1.67

R2

R1

) 1

+ 0.33x10–3

R1R2

R1 ) R2