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CS8140 датащи(PDF) 8 Page - Cherry Semiconductor Corporation

номер детали CS8140
подробное описание детали  5V, 500mA Linear Regulator with ENABLE, , and Watchdog RESET
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производитель  CHERRY [Cherry Semiconductor Corporation]
домашняя страница  http://www.cherrycorp.com/
Logo CHERRY - Cherry Semiconductor Corporation

CS8140 датащи(HTML) 8 Page - Cherry Semiconductor Corporation

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8
As long as ENABLE is high or ENABLE is low and the
Watchdog signal is normal, VOUT will be at 5V (typ). If
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and
the IC goes into SLEEP mode. Only the ENABLE circuitry
in the IC remains powered up, drawing a quiescent cur-
rent of 250µA.
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
lead (Figure 3) until the correct Watchdog input
signal reappears at the lead (ENABLE = HIGH).
The lower and upper window threshold limits of the
watchdog function are set by the value of CDELAY. The lim-
its are determined according to the following equations for
the CS8140:
(a)
tWDILOWER = (1.3 x 105)CDELAY or
fWDI(LOWER) = (7.69 x 10-6)CDELAY-1
(b)
tWDI(UPPER) = (3.82 x 10-4)CDELAY or
fWDI(UPPER) = (2.62 x 10-5)CDELAY-1
For the CS8141 the lower limit is determined by the equa-
tions in (a) above.
The capacitor CDELAY also determines the frequency of the
signal and the POWER-ON-
(POR) delay
period.
Function
The
function is activated when the Watchdog sig-
nal is outside of its preset window (Figure 3), when the
regulator is in its power up state (Figure 4a) or when VOUT
drops below VOUT -4.5% for more than 2µs (Figure 4b.)
If the Watchdog signal falls outside of the preset voltage
and frequency window, a frequency programmable pulse
train is generated at the
lead (Figure 3) until the
correct Watchdog input signal reappears at the lead. The
duration of the
pulse is determined by CDELAY
according to the following equation:
tWDI(
) = (1 x10
4)CDELAY
4a: Power
and Power Down
4b: Undervoltage Triggered
If an undervoltage condition exists, the voltage on the
lead goes low and the delay capacitor, CDELAY, is
discharged.
remains low until output is in regula-
tion, the voltage on CDELAY exceeds the upper switching
threshold and the Watchdog input signal is within its set
window limits (Figure 4). The delay after the output is in
regulation is:
tPOR(typ) = (4.75 x 105) CDELAY
The
delay circuit is also programmed with the
external cap CDELAY.
The output of the reset circuit is an open collector NPN.
is operational down to VOUT = 1V. Both
and
its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
RESET
RESET
RESET
RESET
RESET
RESET
VOUT
VOUT -4.5%
<2
mS
RESET
5V
tPOR
³2ms
RESET
VOUT
VR
HI
VR
LO
VR
LO
tPOR
RESET
VR
PEAK
RESET Circuit Waveforms with Delays Indicated
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
Circuit Description: continued
Application Notes
The CS8140 with its unique integration of linear regulator
and control features:
, ENABLE and WATCHDOG,
provides a single IC solution for a microprocessor power
supply. The reset delay, reset duration and watchdog fre-
quency limits are all determined by a single capacitor. For
a particular microprocessor the overriding requirement is
usually the reset delay (also known as power on reset).
The capacitor is chosen to meet this requirement and the
reset duration and watchdog frequency follow.
The reset delay is given by:
tPOR(typ) = (4.75 x 105)CDELAY
Assume that the reset delay must be 200ms minimum.
From the CS8140 data sheet the reset delay has a ±37% tol-
erance due to the regulator.
Assume the capacitor tolerance is ±10%.
tPOR (min) = (4.75 x 105 x 0.63) x CDELAY x 0.9
CDELAY (min) =
CDELAY = (min) = 0.743 µF
Closest standard value is 0.82µF.
Minimum and maximum delays using 0.82µF are 220ms
and 586ms.
tPOR (min)
2.69 x 105
RESET
CS8140 Design Example


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