Parameter

Symbol

Min

Typ

Max

Units

Audio ADC’s & DAC’s Sample Rate

Fs

4

-

50

kHz

MCLK Frequency

(MCLK = 256, 384, or 512 Fs)

1.024

-

26

MHz

MCLK Pulse Width High

MCLK = 512 Fs

MCLK = 384 Fs

MCLK = 256 Fs

10

21

31

-

-

-

-

-

-

ns

ns

ns

MCLK Pulse Width Low

MCLK = 512 Fs

MCLK = 384 Fs

MCLK = 256 Fs

10

21

31

-

-

-

-

-

-

ns

ns

ns

MCLK Jitter Tolerance

-

500

-

ps RMS

RST Low Time

(Note 8)

10

-

-

ms

SCLK Falling edge to SDOUT output valid (DSCK=0)

--

1

(384

)Fs

+ 20

ns

LRCK edge to MSB valid

-

-

25

ns

SDIN Setup Time Before SCLK Rising Edge

(DSCK=0)

-

-

25

ns

SDIN Hold Time After SCLK Rising Edge

(DSCK=0)

-

-

25

ns

SCLK Period

1

(128

--

ns

SCLK High Time

40

-

-

ns

SCLK Low Time

40

-

-

ns

SCLK Rising to LRCK Edge

(DSCK=0)

20

-

-

ns

LRCK Edge to SCLK Rising

(DSCK=0)

40

-

-

ns

Notes:

8. After powering up the CS4222, PDN should be held low for 10 ms to allow the power supply

to settle.

sckh

sckl

sckw

t

t

t

MSB

MSB-1

*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.

tdpd

SDOUT

LRCK

SCLK*

SDIN

dh

t

ds

t

lrpd

t

lrcks

t

lrckd

t

Serial Audio Port Data I/O timing

CS4222

4

DS236PP3