поискавой системы для электроныых деталей |
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LM3880 датащи(PDF) 8 Page - Texas Instruments |
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LM3880 датащи(HTML) 8 Page - Texas Instruments |
8 / 20 page EN FLAG1 td1 tenable_delay = 1.25V x CEN 7 PA 1.25V - + 7 PA Enable CEN EN LM3880, LM3880Q SNVS451H – AUGUST 2006 – REVISED JULY 2011 www.ti.com The timing sequence of the LM3880 is controlled entirely by the enable (EN) pin. Upon power up, all the flags are held low until this precision enable is pulled high. After the EN pin is asserted, the power up sequence will commence. An internal counter will delay the first flag (FLAG1) from rising until a fixed time period has expired. Upon the release of the first flag another timer will begin to delay the release of the second flag (FLAG2). This process repeats until all three flags have sequentially been released. The three timers that control the delays are all independent of each other and can be individually programmed if needed. (See custom sequencer section). The power down sequence is the same as power-up, but in reverse. When EN pin is de-asserted a timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a sequential manner after their appropriate delays. The three timers that are used to control the power down scheme can also be individually programmed and are completely independent of the power up timers. Additional sequence patterns are also available in addition to customizable timers. For more information see the custom sequencer section. PART OPERATION The timing sequence of the LM3880 is controlled by the assertion of the enable signal. The enable pin is designed with an internal comparator, referenced to a bandgap voltage (1.25V), to provide a precision threshold. This allows a delayed timing to be externally set using a capacitor or to start the sequencing based on a certain event, such as a line voltage reaching 90% of nominal. For an additional delayed sequence from the rail powering VCC, simply attach a capacitor to the EN pin as shown below. Figure 5. Cap Timing Using the internal pull-up current source to charge the external capacitor (CEN) the enable pin delay can be calculated by the equation below: (1) A resistor divider can also be used to enable the LM3880 based on a certain voltage threshold. Care needs to be taken when sizing the resistor divider to include the effects of the internal current source. One of the features of the enable pin is that it provides glitch free operation. The first timer will start counting at a rising threshold, but will always reset if the enable pin is de-asserted before the first output flag is released. This can be shown in the timing diagram below: Figure 6. EN Glitch 8 Submit Documentation Feedback Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880Q |
Аналогичный номер детали - LM3880_14 |
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Аналогичное описание - LM3880_14 |
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