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TSB42AC3 датащи(PDF) 1 Page - Texas Instruments

номер детали TSB42AC3
подробное описание детали  Overview of TSB42AC3
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

TSB42AC3 датащи(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION
TSB42AC3
SLLA220 – JUNE 2006
Overview of TSB42AC3
The TSB42AC3 has a 32-bit, 50-MHz host interface,
which makes connection to most 32-bit hosts fairly
50-MHz Host Interface Frequency Allows
easy. The LLC also provides the capability to receive
Direct Connection to Host With Bus Speeds
status from the PHY and to access the PHY control
up to 50 MHz
and status registers by the application software.
Programmable 10K Byte Total for
An internal 10K-byte memory is provided that can be
Asynchronous, Isochronous, and General
configured as multiple variable-size FIFOs and
Receive FIFO
eliminates the need for external FIFOs. Separate
Separate ACK FIFO Register Decreases
FIFOs
can
be
user
configured
to
support
ACK-tracking Burden on the Host
asynchronous transmit, isochronous transmit, and
general 1394 receive transfer operations. These
Additional Programmable Status Output to
functions are accomplished by appropriately sizing
Pins, Including cd and paccom Bits to Aid
the
asynchronous
transmit
FIFO
(ATF)
and
External DMA
isochronous transmit FIFO (ITF). Once the ATF and
Supports 1394 Transfer Rates of 100, 200,
ITF size are programmed, the remaining memory
and 400 Mbit/s in Cable Environment
space is assigned to the general receive FIFO
(GRF).
Supports 1394 Transfer Rates of 50 and 100
Mbit/s in Backplane Environment
The TSB42AC3 has a separate ACK FIFO register
Generic 32-Bit Host Bus Interface
that is capable of retaining up to six acknowledges
returned by external nodes in response to the
Completely Software Compatible With the
asynchronous
packets
transmitted
from
the
TSB12LV01B
TSB42AC3. This allows host software to load
IEEE 1149.1 JTAG Interface to Support Board
multiple asynchronous packets in the ATF, then
Level Scan Testing
return at a later time to retrieve and process the
acknowledges
returned
from
the
receiving
Operates from a 3.3-V Power Supply
destination nodes.
Support Provisions of IEEE 1394–1995 (1394)
Standard for High-Performance Serial Bus
New status bits were added to the programmable
output status pins. The start/end of packet bit (cd bit)
High Performance 100-Pin TQFP Package
and the packet complete (paccom bit) may now be
brought out to a pin for control of external hardware.
The TSB42AC3 is a 1394-1995 general purpose link
NOTE:
layer ideal for a wide-range of applications, including
motion control, motor control, video, and process
This
product
is
for
control. The TSB42AC3 provides a high-performance
high-volume
applications
interface with the capability of transferring data
only.
For
a
complete
between the 32-bit host controller and the 1394
datasheet
or
more
PHY-link interface. The 1394 PHY-link interface
information
contact
provides the connection to the 1394 physical layer
support@ti.com.
device (PHY) and is supported by the link-layer
controller (LLC). The LLC provides the control for
transmitting and receiving 1394 packet data between
the FIFO and PHY-link interface at rates of 50
(backplane only), 100, 200, and 400 Mbit/s.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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