поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

TSB41BA3B-EP датащи(PDF) 9 Page - Texas Instruments

Click here to check the latest version.
номер детали TSB41BA3B-EP
подробное описание детали  IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
Download  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

TSB41BA3B-EP датащи(HTML) 9 Page - Texas Instruments

Back Button TSB41BA3B-EP Datasheet HTML 5Page - Texas Instruments TSB41BA3B-EP Datasheet HTML 6Page - Texas Instruments TSB41BA3B-EP Datasheet HTML 7Page - Texas Instruments TSB41BA3B-EP Datasheet HTML 8Page - Texas Instruments TSB41BA3B-EP Datasheet HTML 9Page - Texas Instruments TSB41BA3B-EP Datasheet HTML 10Page - Texas Instruments TSB41BA3B-EP Datasheet HTML 11Page - Texas Instruments TSB41BA3B-EP Datasheet HTML 12Page - Texas Instruments TSB41BA3B-EP Datasheet HTML 13Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 68 page
background image
TSB41BA3BEP
IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS362—MAY 2006
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
TERMINAL
NAME
TYPE
PFP
NO.
I/O
DESCRIPTION
LCLK_PMC
CMOS
7
I
Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to the PHY.
On hardware reset this terminal is sampled to determine the power management control (PMC)
mode.
LCLK_PMC
LPS
BMODE
Mode
H
L
H
No LLC (PMC mode)
n/c†
lps
L
Legacy LLC
LCLK_PMC‡
lps
H
Beta LLC
† internal pulldown on LCLK_PMC
‡ LCLK_PMC from LLC normally low during reset
In PMC mode, because no LLC is attached, the data lines (D7−D0) are available to indicate
power states. In PMC mode, the following signals are output:
D0—port 0 cable-power disable (see Note 1)
− D1—port 1 cable-power disable (port in sleep or disabled)
− D2—port 2 cable-power disable (port in sleep or disabled)
− D6—All ports cable-power disable (all ports in sleep/disable) logical AND of bits 0−2
− D3−D5 and D7 are reserved for future use.
Note 1: The cable-power disable is asserted when the port is either:
− Hard-disabled (both the disabled and hard-disabled bits are set)
− Sleep-disabled (both the disabled and sleep_enable bits are set)
− Disconnected
− Asleep
− Connected in DS mode, but nonactive (that is, suspended or disabled)
Otherwise, the cable-powered disable output is deasserted (that is, cable power enabled) when
the port is dc-connected or active. A bus holder is built into this terminal.
LPS
CMOS
80
I
Link power status input. This terminal monitors the active/power status of the link-layer controller
(LLC) and controls the state of the PHY-LLC interface. This terminal must be connected to either the
VDD supplying the LLC through an approximately 1-kΩ resistor or to a pulsed output which is active
when the LLC is powered. A pulsed signal must be used when an isolation barrier exists between the
LLC and PHY (see Figure 8).
The LPS input is considered inactive if it is sampled low by the PHY for more than a LPS_RESET time
(~2.6
µs) and is considered active otherwise (that is, asserted steady high or an oscillating signal with
a low time less than 2.6
µs). The LPS input must be high for at least 22 ns to be observed as high by
the PHY.
When the TSB41BA3B-EP detects that the LPS input is inactive, it places the PHY-LLC interface into
a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D (D0 to D7) outputs are
held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If
the LPS input remains low for more than a LPS_DISABLE time (~26
µs), then the PHY-LLC interface
is put into a low-power disabled state in which the PCLK output is also held inactive.
The LLC state that is communicated in the self-ID packet is considered active only if both the LPS
input is active and the LCtrl register bit is set to 1. The LLC state that is communicated in the self-ID
packet is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0.
LREQ
CMOS
3
I
LLC request input. The LLC uses this input to initiate a service request to the TSB41BA3B-EP. A bus
holder is built into this terminal.
PCLK
CMOS
5
O
PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when
the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a
49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is
in legacy 1394a-2000 (BMODE input deasserted).


Аналогичный номер детали - TSB41BA3B-EP

производительномер деталидатащиподробное описание детали
logo
Texas Instruments
TSB41BA3B-EP TI1-TSB41BA3B-EP Datasheet
1,023Kb / 67P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER  
More results

Аналогичное описание - TSB41BA3B-EP

производительномер деталидатащиподробное описание детали
logo
Texas Instruments
TSB81BA3IPFPEP TI1-TSB81BA3IPFPEP Datasheet
711Kb / 57P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3B TI-TSB41BA3B Datasheet
1Mb / 67P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB81BA3 TI-TSB81BA3 Datasheet
810Kb / 57P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3A TI1-TSB41BA3A_16 Datasheet
222Kb / 11P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3D TI-TSB41BA3D Datasheet
875Kb / 59P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3D TI1-TSB41BA3D_14 Datasheet
754Kb / 60P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3A-EP TI1-TSB41BA3A-EP_14 Datasheet
768Kb / 69P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3B-EP TI1-TSB41BA3B-EP Datasheet
1,023Kb / 67P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER  
TSB81BA3D TI1-TSB81BA3D_12 Datasheet
682Kb / 61P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB81BA3E TI-TSB81BA3E Datasheet
887Kb / 57P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB81BA3-EP TI-TSB81BA3-EP Datasheet
764Kb / 56P
[Old version datasheet]   IEEE 1394B THREE-PORT CABLE TRANSCEIVER/ARBITER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


датащи скачать

Go To PDF Page


ссылки URL




Конфиденциальность
ALLDATASHEETRU.COM
Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com