TLC540I, TLC541I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS065B – OCTOBER 1983 – REVISED JUNE 2001

9

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

The TLC540 and TLC541 are each complete data acquisition systems on a single chip. They include such functions

as analog multiplexer, sample and hold, 8-bit A/D converter, data and control registers, and control logic. For flexibility

and access speed, there are four control inputs [two clocks, chip select (CS), and address]. These control inputs and

a TTL-compatible 3-state output are intended for serial communications with a microprocessor or microcomputer.

With judicious interface timing, with TLC540 a conversion can be completed in 9

µs, while complete input-

conversion-output cycles can be repeated every 13

µs. With TLC541 a conversion can be completed in 17 µs, while

complete input-conversion-output cycles are repeated every 25

µs. Furthermore, this fast conversion can be

executed on any of 11 inputs or its built-in self-test and in any order desired by the controlling processor.

The system and I/O clocks are normally used independently and do not require any special speed or phase

relationships between them. This independence simplifies the hardware and software control tasks for the device.

Once a clock signal within the specification range is applied to SYSTEM CLOCK, the control hardware and software

need only be concerned with addressing the desired analog channel, reading the previous conversion result, and

starting the conversion by using I/O CLOCK. SYSTEM CLOCK will drive the conversion crunching circuitry so that

the control hardware and software need not be concerned with this task.

When CS is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature

allows each of these terminals, with the exception of CS, to share a control logic point with their counterpart terminals

on additional A/D devices when additional TLC540/541 devices are used. In this way, the above feature serves to

minimize the required control logic terminals when using multiple A/D devices.

The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain

the conversion result. A normal control sequence is:

1.

CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges

and then a falling edge of SYSTEM CLOCK after a low CS transition, before the low transition is recognized.

This technique is used to protect the device against noise when the device is used in a noisy environment.

The MSB of the previous conversion result automatically appears on DATA OUT.

2.

A new positive-logic multiplexer address is shifted in on the first four rising edges of I/O CLOCK. The MSB

of the address is shifted in first. The negative edges of these four I/O clock pulses shift out the second, third,

fourth, and fifth most significant bits of the previous conversion result. The on-chip sample and hold begins

sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically

involves the charging of internal capacitors to the level of the analog input voltage.

3.

Three clock cycles are then applied to I/O CLOCK and the sixth, seventh, and eighth conversion bits are

shifted out on the negative edges of these clock cycles.

4.

The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the

analog sampling process and initiates the hold function. Conversion is then performed during the next 36

system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low

for at least 36 system clock cycles to allow for the conversion function.

CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple

conversion, special care must be exercised to prevent noise glitches on I/O CLOCK. If glitches occur on I/O CLOCK,

the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, if CS is taken

high, it must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset condition,

which aborts the conversion in progress.

A new conversion can be started and the ongoing conversion simultaneously aborted by performing steps 1 through

4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and

not the ongoing conversion.