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ADC12132 датащи(PDF) 11 Page - Texas Instruments

номер детали ADC12132
подробное описание детали  ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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ADC12132 датащи(HTML) 11 Page - Texas Instruments

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ADC12130, ADC12132, ADC12138
www.ti.com
SNAS098G – MARCH 2000 – REVISED MARCH 2013
AC Electrical Characteristics (continued)
The following specifications apply for (V
+ = V
A+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+ = V
A+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), VREF− = 0V, 12-bit + sign conversion mode
(1), source impedance for analog inputs, V
REF− and VREF+ ≤ 25Ω,
fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25°C.
(2) (Continued)
Units
Parameter
Test Conditions
Typical (3)
Limits (4)
(Limits)
Hardware Power-Up Time, Time from PD
tHPU
500
700
μs (max)
Falling Edge to EOC Rising Edge
Software Power-Up Time, Time from Serial
tSPU
500
700
μs (max)
Data Clock Falling Edge to EOC Rising Edge
Access Time Delay from CS Falling Edge to
tACC
25
60
ns (max)
DO Data Valid
Set-Up Time of CS Falling Edge to Serial Data
tSET-UP
50
ns (min)
Clock Rising Edge
Delay from SCLK Falling Edge to CS Falling
tDELAY
0
5
ns (min)
Edge
t1H, t0H
Delay from CS Rising Edge to DO TRI-STATE
RL = 3k, CL = 100 pF
70
100
ns (max)
DI Hold Time from Serial Data Clock Rising
tHDI
5
15
ns (max)
Edge
DI Set-Up Time from Serial Data Clock Rising
tSDI
5
10
ns (min)
Edge
DO Hold Time from Serial Data Clock Falling
35
65
ns (max)
tHDO
RL = 3k, CL = 100 pF
Edge
5
ns (min)
Delay from Serial Data Clock Falling Edge to
tDDO
50
90
ns (max)
DO Data Valid
DO Rise Time, TRI-STATE to High DO Rise
10
40
ns (max)
tRDO
RL = 3k, CL = 100 pF
Time, Low to High
10
40
ns (max)
DO Fall Time, TRI-STATE to Low DO Fall
15
40
ns (max)
tFDO
RL = 3k, CL = 100 pF
Time, High to Low
15
40
ns (max)
Delay from CS Falling Edge to DOR Falling
tCD
45
80
ns (max)
Edge
Delay from Serial Data Clock Falling Edge to
tSD
45
80
ns (max)
DOR Rising Edge
CIN
Capacitance of Logic Inputs
20
pF
COUT
Capacitance of Logic Outputs
20
pF
(3)
Typical figures are at TJ = TA = 25°C and represent most likely parametric norm.
(4)
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
Copyright © 2000–2013, Texas Instruments Incorporated
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Product Folder Links: ADC12130 ADC12132 ADC12138


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