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ADC08500 датащи(PDF) 9 Page - Texas Instruments

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номер детали ADC08500
подробное описание детали  ADC08500 High Performance, Low Power 8-Bit, 500 MSPS A/D Converter
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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I / O
GND
V
A
TO INTERNAL
CIRCUITRY
ADC08500
www.ti.com
SNAS373E – MAY 2007 – REVISED APRIL 2013
Converter Electrical Characteristics
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870 mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle,
VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. See
(1) (2)
Units
Symbol
Parameter
Conditions
Typical (3)
Limits (3)
(Limits)
STATIC CONVERTER CHARACTERISTICS
DC Coupled, 1MHz Sine Wave
INL
Integral Non-Linearity
±0.3
±0.9
LSB (max)
OverRanged
DC Coupled, 1MHz Sine Wave Over
DNL
Differential Non-Linearity
±0.15
±0.6
LSB (max)
Ranged
Resolution with No Missing Codes
8
Bits
−1.5
LSB (min)
VOFF
Offset Error
-0.5
0.5
LSB (max)
VOFF_ADJ
Input Offset Adjustment Range
Extended Control Mode
±45
mV
PFSE
Positive Full-Scale Error (4)
±25
mV (max)
NFSE
Negative Full-Scale Error (4)
±25
mV (max)
FS_ADJ
Full-Scale Adjustment Range
Extended Control Mode
±20
±15
%FS
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth
1.7
GHz
B.E.R.
Bit Error Rate
10-18
Error/Sample
Gain Flatness
d.c. to 500 MHz
±0.5
dBFS
fIN = 50 MHz, VIN = FSR − 0.5 dB
7.5
Bits
ENOB
Effective Number of Bits
fIN = 124 MHz, VIN = FSR − 0.5 dB
7.5
7.1
Bits (min)
fIN = 248 MHz, VIN = FSR − 0.5 dB
7.5
7.1
Bits (min)
fIN = 50 MHz, VIN = FSR − 0.5 dB
47
dB
SINAD
Signal-to-Noise Plus Distortion Ratio
fIN = 124 MHz, VIN = FSR − 0.5 dB
47
44.5
dB (min)
fIN = 248 MHz, VIN = FSR − 0.5 dB
47
44.5
dB (min)
fIN = 50 MHz, VIN = FSR − 0.5 dB
48
dB
SNR
Signal-to-Noise Ratio
fIN = 124 MHz, VIN = FSR − 0.5 dB
47.5
45.3
dB (min)
fIN = 248 MHz, VIN = FSR − 0.5 dB
47.5
45.3
dB (min)
fIN = 50 MHz, VIN = FSR − 0.5 dB
-55
dB
THD
Total Harmonic Distortion
fIN = 124 MHz, VIN = FSR − 0.5 dB
-56
−47.5
dB (max)
fIN = 248 MHz, VIN = FSR − 0.5 dB
-56
−47.5
dB (max)
(1)
The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
(2)
To ensure accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded.
(3)
Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
(4)
Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for
this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Transfer Characteristic Figure 4. For
relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.
Copyright © 2007–2013, Texas Instruments Incorporated
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