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AD1876 датащи(PDF) 10 Page - Analog Devices |
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AD1876 датащи(HTML) 10 Page - Analog Devices |
10 / 12 page AD1876 REV. A –10– lessened. In summary, system performance is optimized by run- ning the AD1876 at or near its maximum sampling rate of 100 kHz and digitally filtering the resulting spectrum to elimi- nate undesired frequencies. DSP INTERFACE Figure 8 illustrates the use of the Analog Devices ADSP-2101 digital signal processor with the AD1876. The ADSP-2101 FO (flag out) pin of serial port 1 (SPORT 1) is connected to the SAMPLE line and is used to control acquisition of data. The ADSP-2101 timer is used to provide precise timing of the FO pin. ADSP-2101 FO AD1876 SAMPLE SERIAL PORT Ø CLK D BUSY SCLK0 DR0 RFS0 DT0 TFS0 OUT Figure 8. ADSP-2101 Interface The SCLK pin of the ADSP-2101 SPORT0 provides the CLK input for the AD1876. The clock should be programmed to be approximately 2 MHz to comply with AD1876 specifications. To minimize digital feedthrough, the clock should be disabled (by setting Bit 14 in SPORT0 control register to 0) during data acquisition. Since the clock floats when disabled, a pull-down resistor of 12 k–15 k Ω should be connected to SCLK to ensure it will be LOW at the falling edge of SAMPLE. To maximize the conversion rate, the serial clock should be enabled immedi- ately after SAMPLE is brought LOW (hold mode). The AD1876 BUSY signal is connected to RF0 to notify SPORT0 when a new data word is coming. SPORT0 should be configured in normal, external, noninverting framing mode and can be programmed to generate an interrupt after the last data bit is received. To maximize the conversion rate, SAMPLE should be brought HIGH immediately after the last data bit is received. SIGNAL PROCESSING An audio spectrum analyzer can be produced by combining an AD1876 and an ADSP-2101 signal processing microcomputer. This system can analyze signals from dc to 50 kHz depending on the sample rate. This is ideal for applications such as audio analysis, but could also be applied to vibration analysis as well. AUDIO DELAY LINE A high performance, 16-bit stereo delay line can be constructed from two AD1876 audio ADCs, a signal processing microcom- puter and two AD1856 audio DACs. Depending on the length of the internal buffer which produces the delay, a variable delay is possible. Other applications are also possible with only a change in software. For example, a reverb or echo effect could be generated as well. AD1876 AND SM5805 DIGITAL FILTER @ 2 FS A simple method for generating the required signals for the AD1876 is to connect one or more AD1876s to an NPC SM5805 digital filter. This device supplies all signals required to operate the AD1876 at a 96 kHz sample rate, which is 2 × F S for audio applications. To minimize group delay distortion, the input to the AD1876 is filtered only by a low order analog filter. The AD1876 samples the output of the filter at 2 FS (96 kHz). To prevent aliasing, the SM5805 filters the data with a sharp, linear phase filter rolling off at 0.5 FS. The resulting data is decimated to a sample rate of 48 kSPS. Interfacing the two chips is straightforward, as shown in Figure 9. The start signal for the AD1876 (for 96 kSPS operation) is provided by the S/H pin of the SM5805, and CLK is derived from the BCC pin. Figure 10 illustrates the corresponding tim- ing diagram. LEFT CHANNEL INPUT RIGHT CHANNEL INPUT *ADDITIONAL PINS OMITTED FOR CLARITY LEFT OPEN OR TIED TO +5V AD1876* D CLK SAMPLE OUT VIN 10 3 2 1 AD1876* D CLK SAMPLE OUT VIN 10 3 2 1 7 5 10 11 15 SH BBC IBLK 16 18 8 4 DINL DOL DINR ISLB IBPOL U/O OFB LRCK DOR 25 24 SM5805* 612 IPARA DECIMATED DATA, LEFT DECIMATED DATA, RIGHT 1F (48kHz) CLOCK S Figure 9. AD1876 and SM5805 Digital Filter MSB SH OUTPUT BBC OUTPUT DINL DINR MSB Lm Rm Lm + 1 Rm + 1 234 5 6 7 8 910 11 12 13 14 15 17 1 234 5 6 7 8 910 11 12 13 14 15 234 5 6 7 89 10 11 12 13 14 15 234 5 6 7 8 910 11 12 13 14 15 MSB MSB LSB LSB LSB LSB 1/f (f = 48kHz) s s Figure 10. SM5805 Timing Diagram OBSOLETE |
Аналогичный номер детали - AD1876_15 |
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Аналогичное описание - AD1876_15 |
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