AD1803

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

2

3

4

5

6

7

8

9

10

21

22

23

24

20

19

18

17

16

15

14

13

12

11

AD1803

TOP VIEW

(Not to Scale)

G[5]

DGND

G[6]

DVDD

G[7]

XTALO

AVDD

XTALI

Tx

BIT_CLK

AGND

SDATA_IN

SDATA_OUT

FILT

SYNC

Rx

RESET

G[1]/MIC

G[4]/MOUT

G[0]

G[3]/WAKE

G[2]

Figure 9. Pin Configuration

Table 6. Pin Function Descriptions

Mnemonic

Pin No.

I/O

Description

ANALOG SIGNALS

DVDD

DGND

AVDD

AGND

Rx

Tx

FILT

3

2

21

19

16

20

17

18

I

I

I

I

I

O

I

I

Digital Supply. Range: 5.0 V ± 10% or 3.3 V ± 10% (independent of AVDD).

Digital Ground. Must be at same potential as AGND.

Analog Supply. Range is 5.5 V through 3.0 V (independent of DVDD).

Analog Ground. Must be at same potential as DGND.

Receive (ADC) input.

Transmit (DAC) output.

ADC Filter Bypass. Requires 1 μF capacitor to AGND.

Voltage Reference. Requires 1 μF capacitor to AGND.

CLOCK SIGNALS

XTALI

XTALO

CLK_OUT

5

4

1

I

O

O

Crystal or Clock Input (12.288 MHz, 24.576 MHz, or 32.768 MHz). This clock input is neces­

sary only if the AD1803 is configured in either AC '97 primary or DSP mode, or if a wake

interrupt from an event is required (in any mode). This pin must be tied to DVDD or DGND

(not floated) when clock input is not necessary. If a crystal is used, it must be parallel

resonant first harmonic, and tied between this pin and the XTALO pin with load capacitance

specified by the crystal supplier. See the XTAL1 bit and the XTAL0 bit in Register 0x5C for

further details.

Crystal Output. This pin should be floated when a crystal is not used.

Buffered version of clock present on the XTALI pin, unless disabled. See the CLKED bit and

CLKEA bit in Register 0x5C for further details.

SERIAL INTERFACE SIGNALS1

RESET

BIT_CLK

SYNC

SDATA_IN

SDATA_OUT

10

6

9

7

8

I

I/O

I/O

O

I

Active Low Power-Down. Level of power-down is determined by bits in Register 0x5C. This

pin must be asserted (driven low) as power is first applied until the supply is stable. The

AD1803 is RESET exclusively by an internal power-on RESET circuit.

Serial Data Clock. Output if the AD1803 configured in AC '97 primary or DSP mode. Input if

the AD1803 is configured in any AC '97 secondary mode.

Serial Data Frame Sync. Output if the AD1803 is configured in DSP mode. Input if the

AD1803 is configured in any AC '97 mode.

Serial Data Output from AD1803.

Serial Data Input to AD1803.

Rev. A | Page 9 of 32