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TP7C51BH датащи(PDF) 5 Page - Intel Corporation

номер детали TP7C51BH
подробное описание детали  CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

TP7C51BH датащи(HTML) 5 Page - Intel Corporation

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AUTOMOTIVE 80C31BH80C51BH87C51
Port 3 also serves the functions of various special
features of the MCS 51 microcontroller family as
listed below
Pin
Name
Alternate Function
P30
RXD
Serial Input Line
P31
TXD
Serial Output Line
P32
INT0
External Interrupt 0
P33
INT1
External Interrupt 1
P34
T0
Timer 0 External Input
P35
T1
Timer 1 External Input
P36
WR
External Data Memory Write Strobe
P37
RD
External Data Memory Read Strobe
Port 3 also receives some control signals for
EPROM programming and program verification
RESET
Reset input A logic high on this pin for two
machine cycles while the oscillator is running resets
the device An internal pulldown resistor permits a
power-on reset to be generated using only an exter-
nal capacitor to VCC
ALEPROG (EPROM Only)
Address Latch Enable
output signal for latching the low byte of the address
during accesses to external memory This pin is also
the program pulse input (PROG) during EPROM pro-
gramming
In normal operation ALE is emitted at a constant
rate of 16 the oscillator frequency and may be
used for external timing or clocking purposes Note
however that one ALE pulse is skipped during each
access to external Data Memory
PSEN
Program Store Enable is the Read strobe
to
External
Program
Memory
When
the
87C5180C51BH is executing from Internal Program
Memory PSEN is inactive (high) When the device is
executing code from External Program Memory
PSEN is activated twice each machine cycle except
that two PSEN activations are skipped during each
access to External Data Memory
EA VPP External Access enable EA must be
strapped
to
VSS
in
order
to
enable
the
87C5180C51BH to fetch code from External Pro-
gram Memory locations starting at 0000H up to
0FFFFH
Note however that if either of the Lock
Bits is programmed the logic level at EA is internally
latched during reset
(EPROM only)
EA must be strapped to VCC for internal program
execution
VPP (EPROM Only) This pin also receives the
1275V programming supply voltage (VPP) during
EPROM programming
270419 – 5
Figure 4 Using the On-Chip Oscillator
270419 – 6
Figure 5 External Clock Drive
XTAL1
Input to the inverting oscillator amplifier and
input to the internal clock generating circuits
XTAL2
Output from the inverting oscillator amplifi-
er
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 4
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 is left uncon-
nected as shown in Figure 5 There are no require-
ments on the duty cycle of the external clock signal
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop but minimum and
maximum high and low times specified on the Data-
sheet must be observed
IDLE MODE
In Idle Mode the CPU puts itself to sleep while all
the on-chip peripherals remain active The mode is
invoked by software The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode The Idle Mode can be
terminated by any enabled interrupt or by a hard-
ware reset
It should be noted that when Idle is terminated by a
hardware reset the device normally resumes pro-
gram execution from where it left off up to two ma-
chine cycles before the internal reset algorithm
takes control On-chip hardware inhibits access to
5


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