поискавой системы для электроныых деталей |
|
AD5346 датащи(PDF) 4 Page - Analog Devices |
|
AD5346 датащи(HTML) 4 Page - Analog Devices |
4 / 24 page AD5346/AD5347/AD5348 Rev. 0 | Page 4 of 24 B Version1 Parameter2 Min Typ Max Unit Conditions/Comments LOGIC OUTPUTS6 VDD = 4.5 V to 5.5 V Output Low Voltage, VOL 0.4 V ISINK = 200 µA Output High Voltage, VOH VDD – 1 V ISOURCE = 200 µA VDD = 2.5 V to 3.6 V Output Low Voltage, VOL 0.4 V ISINK = 200 µA Output High Voltage, VOH VDD – 0.5 V ISOURCE = 200 µA POWER REQUIREMENTS VDD 2.5 5.5 V IDD (Normal Mode) VIH = VDD, VIL = GND VDD = 4.5 V to 5.5 V 1 1.65 mA All DACs in unbuffered mode. In buffered mode, VDD = 2.5 V to 3.6 V 0.8 1.4 mA extra current is typically x µA per DAC, where x = 5 µA + VREF/RDAC IDD (Power-Down Mode) VIH = VDD, VIL = GND VDD = 4.5 V to 5.5 V 0.4 1 µA VDD = 2.5 V to 3.6 V 0.12 1 µA See footnotes after the AC Characteristics table. AC CHARACTERISTICS6 Table 2. VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted B Version1 Parameter2 Min Typ Max Unit Conditions/Comments Output Voltage Settling Time VREF = 2 V AD5346 6 8 µs 1/4 scale to 3/4 scale change (40 H to C0 H) AD5347 7 9 µs 1/4 scale to 3/4 scale change (100 H to 300 H) AD5348 8 10 µs 1/4 scale to 3/4 scale change (400 H to C00 H) Slew Rate 0.7 V/µs Major Code Transition Glitch Energy 8 nV-s 1 LSB change around major carry Digital Feedthrough 0.5 nV-s Digital Crosstalk 1 nV-s Analog Crosstalk 1 nV-s DAC-to-DAC Crosstalk 3.5 nV-s Multiplying Bandwidth 200 kHz VREF = 2 V ±0.1 V p-p; unbuffered mode Total Harmonic Distortion –70 dB VREF = 2. V ±0.1 V p-p; frequency = 10 kHz; unbuffered mode 1 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. 2 See Terminology section. 3 Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095). 4 DC specifications tested with outputs unloaded. 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and the offset plus gain error must be positive. IOH IOL TO OUTPUT PIN VOH(min) + VOL(max) 2 CL 50pF 200 µA 200 µA Figure 2. Load Circuit for Digital Output Timing Specifications |
Аналогичный номер детали - AD5346_15 |
|
Аналогичное описание - AD5346_15 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |