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CD82C237 датащи(PDF) 10 Page - Intersil Corporation |
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CD82C237 датащи(HTML) 10 Page - Intersil Corporation |
10 / 25 page 4-157 82C237 Mask Register - Each channel has associated with it a mask bit which can be set to disable an incoming DREQ. Each mask bit is set when its associated channel produces an EOP if the channel is not programmed to Autoinitialize. Each bit of the 4-bit Mask register may also be set or cleared separately or simultaneously under software control. The entire register is also set by a RESET or Master clear. This disables all hard- ware DMA requests until a Clear Mask Register instruction allows them to occur. The instruction to separately set or clear the mask bits is similar in form to that used with the Request register. Refer to the following diagram and Figure 4 for details. When reading the Mask register, bits 4-7 will always read as logical ones, and bits 0-3 will display the mask bits of channels 0-3, respectively. The 4-bits of the mask register may be cleared simultaneously by using the Clear Mask Reg- ister command (see software commands section). All four bits of the Mask register may also be written with a single command. Status Register - The Status register is available to be read out of the 82C237 by the microprocessor. It contains information about the status of the devices at this point. This information includes which channels have reached a terminal count and which channels have pending DMA requests. Bits 0-3 are set every time a TC is reached by that channel or an external EOP is applied. These bits are cleared upon RESET, Master Clear, and on each Status Read. Bits 4-7 are set whenever their corresponding channel is requesting service, regardless of the mask bit state. If the mask bits are set, soft- ware can poll the Status register to determine which channels have DREQs, and selectively clear a mask bit, thus allowing user defined service priority. Status bits 4-7 are updated while the clock is high, and latched on the falling edge. Status Bits 4-7 are cleared upon RESET or Master Clear. Temporary Register - The Temporary register is used to hold data during memory-to-memory transfers. Following the com- pletion of the transfers, the last byte moved can be read by the microprocessor. The Temporary register always contains the last byte transferred in the previous memory-to-memory oper- ation, unless cleared by a RESET or Master Clear. Mask Register 76543210 BIT NUMBER 00 01 10 11 Select channel 0 mask bit Select channel 1 mask bit Select channel 2 mask bit Select channel 3 mask bit 0 1 Clear mask bit Set mask bit 76543210 BIT NUMBER 0 1 Clear channel 0 mask bit Set channel 0 mask bit 0 1 Clear channel 1 mask bit Set channel 1 mask bit 0 1 Clear channel 2 mask bit Set channel 2 mask bit 0 1 Clear channel 3 mask bit Set channel 3 mask bit Don’t Care, Don’t Care, Write All Ones, Read Status Register 76543210 BIT NUMBER 1 Channel 0 has reached TC 1 Channel 1 has reached TC 1 Channel 2 has reached TC 1 Channel 3 has reached TC 1 Channel 0 request 1 Channel 1 request 1 Channel 2 request 1 Channel 3 request OPERATION A3 A2 A1 A0 IOR IOW Read Status Register 100001 Write Command Register 100010 Read Request Register 100101 Write Request Register 100110 Read Command Register 101001 Write Single Mask Bit 101010 Read Mode Register 101101 Write Mode Register 101110 Set First/Last F/F 110001 Clear First/Last F/F 110010 Read Temporary Register 110101 Master Clear 110110 Clear Mode Reg. Counter 111001 Clear Mask Register 111010 Read All Mask Bits 111101 Write All Mask Bits 111110 FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES |
Аналогичный номер детали - CD82C237 |
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Аналогичное описание - CD82C237 |
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