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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD6634 датащи(PDF) 8 Page - Analog Devices |
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AD6634 датащи(HTML) 8 Page - Analog Devices |
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8 / 52 page  REV. 0 –8– AD6634 GENERAL TIMING CHARACTERISTICS1, 2 Test AD6634BBC Parameter (Conditions) Temp Level Min Typ Max Unit CLK TIMING REQUIREMENTS tCLK CLK Period Full I 12.5 ns tCLKL CLK Width Low Full IV 5.6 0.5 × tCLK ns tCLKH CLK Width High Full IV 5.6 0.5 × t CLK ns RESET TIMING REQUIREMENTS tRESL RESET Width Low Full I 30.0 ns INPUT WIDEBAND DATA TIMING REQUIREMENTS tSI Input to ↑CLK Setup Time Full IV 2.0 ns tHI Input to ↑CLK Hold Time Full IV 1.0 ns LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS tDLI ↑CLK to LI (A–A, B; B–A, B) Output Delay Time Full IV 3.3 10.0 ns SYNC TIMING REQUIREMENTS tSS SYNC (A, B, C, D) to ↑CLK Setup Time Full IV 2.0 ns tHS SYNC (A, B, C, D) to ↑CLK Hold Time Full IV 1.0 ns SERIAL PORT CONTROL TIMING REQUIREMENTS SWITCHING CHARACTERISTICS 2 tSCLK SCLK Period Full IV 16 ns tSCLKL SCLK Low Time Full IV 3.0 ns tSCLKH SCLK High Time Full IV 3.0 ns INPUT CHARACTERISTICS tSSI SDI to ↓SCLK Setup Time Full IV 1.0 ns tHSI SDI to ↓SCLK Hold Time Full IV 1.0 ns PARALLEL PORT TIMING REQUIREMENTS (MASTER MODE) SWITCHING CHARACTERISTICS 3 tDPOCLKL ↓CLK to ↑PCLK Delay (Divide by 1) Full IV 6.5 10.5 ns tDPOCLKLL ↓CLK to ↑PCLK Delay (Divide by 2, 4, or 8) Full IV 8.3 14.6 ns tDPREQ ↑CLK to ↑PxREQ Delay 1.0 ns tDPP ↑CLK to Px[15:0] Delay 0.0 ns INPUT CHARACTERISTICS tSPA PxACK to ↓PCLK Setup Time +7.0 ns tHPA PxACK to ↓PCLK Hold Time –3.0 ns PARALLEL PORT TIMING REQUIREMENTS (SLAVE MODE) SWITCHING CHARACTERISTICS 3 tPOCLK PCLK Period Full I 12.5 ns tPOCLKL PCLK Low Period (when PCLK Divisor = 1) Full IV 2.0 0.5 × tPOCLK ns tPOCLKH PCLK High Period (when PCLK Divisor = 1) Full IV 2.0 0.5 × t POCLK ns tDPREQ ↑CLK to ↑PxREQ Delay 10.0 ns tDPP ↑CLK to Px[15:0] Delay 11.0 ns INPUT CHARACTERISTICS tSPA PxACK to ↓PCLK Setup Time 1.0 ns tHPA PxACK to ↓PCLK Hold Time 1.0 ns LINK PORT TIMING REQUIREMENTS SWITCHING CHARACTERISTICS 3 tRDLCLK ↑PCLK to ↑LxCLKOUT Delay Full IV 2.5 ns tFDLCLK ↓PCLK to ↓LxCLKOUT Delay Full IV 0 ns tRLCLKDAT ↑LCLKOUT to Lx[7:0] Delay Full IV 0 2.9 ns tFLCLKDAT ↓LCLKOUT to Lx[7:0] Delay Full IV 0 2.2 ns NOTES 1All Timing Specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V. 2C LOAD = 40 pF on all outputs unless otherwise specified 3The timing parameters for Px[15:0], PxREQ, PxACK, LxCLKOUT, Lx[7:0] apply for port A and B (x stands for A or B). Specifications subject to change without notice. |
Аналогичный номер детали - AD6634_15 |
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Аналогичное описание - AD6634_15 |
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