4-350

FIGURE 6. 82C89 BUS ARBITER SHOWN IN SYSTEM - RESIDENT BUS CONFIGURATION

NOTE: By adding another 82C89 arbiter and connecting its AEN to the 82C88 whose AEN is presently grounded, the processor could have

access to two multi-master buses.

TRANSCEIVER

T

OE

82C86H/

82C87H

(2)

IOB

AEN

82C89

S0

S2

CLK

ANYRQST

BUS

ARBITER

82C84A/85

CLOCK

RDY2

READY

AEN2

RDY1

CLK

80C86

CPU

READY

S0-S2

AD0-AD15

A16-A19

CLK

AEN1

S1

SYSB/

RESB

RESB

DEN

82C88

CLK

S0-S2

IOB

ALE

DT/R

ADDR

LATCH

OE

STB

82C82/

82C83H

(2 OR 3)

ADDR

LATCH

OE

STB

82C82/

82C83H

(2 OR 3)

TRANSCEIVER

OE

T

82C86H/

82C87H

(2)

DEN

82C88

CLK

S0-S2

ALE

DT/R

AEN

PROM

OR

DECODER

OR

CMOS HPL

CEN

STATUS

AEN

CEN

XACK MULTI MASTER

SYSTEM BUS

MULTI MASTER

SYSTEM BUS CONTROL

MULTI MASTER

SYSTEM COMMAND BUS

MULTI MASTER

SYSTEM ADDRESS BUS

MULTI MASTER

SYSTEM DATA BUS

XACK

RESIDENT BUS

RESIDENT

COMMAND BUS

RESIDENT

ADDRESS BUS

RESIDENT

DATA BUS

(NOTE)

82C89