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AD7812 датащи(PDF) 5 Page - Analog Devices |
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AD7812 датащи(HTML) 5 Page - Analog Devices |
5 / 24 page AD7811/AD7812 –5– REV. B PIN FUNCTION DESCRIPTIONS Pin(s) Pin(s) AD7811 AD7812 Mnemonic Description 11 VREF An external reference input can be applied here. When using an external precision reference or VDD the EXTREF bit in the control register must be set to logic one. The external reference input range is 1.2 V to VDD. 22 CREF Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise performance of the on-chip reference. 3, 5–7 3, 5–11 VIN1–VIN4(8) Analog Inputs. The analog input range is 0 V to VREF. 4 4 AGND Analog Ground. Ground reference for track/hold, comparator, on-chip reference and DAC. 8 12 A0 Package Address Pin. This Logic Input can be hardwired high or low. When used in conjunction with the package address bit in the control register this input allows two devices to share the same serial bus. For example a twelve channel solution can be achieved by using the AD7811 and the AD7812 on the same serial bus. 9 13 DGND Digital Ground. Ground reference for digital circuitry. 10 14 TFS Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new control byte should be shifted in on the next 10 falling edges of SCLK. 11 15 RFS Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in the serial interface. It is used to provide compatibility with DSPs which use a continuous serial clock and framing signal. In multipackage applications the RFS Pin can also be used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a rising edge on this input. The counter is reset at the end of a serial read operation. 12 16 DOUT Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial clock. The output enters a High impedance condition on the rising edge of the 11th SCLK pulse. 13 17 DIN Serial Data Input. The control byte is read in at this input. In order to complete a serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are shifted in—see Serial Interface section. 14 18 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK. 15 19 CONVST Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold Mode on the falling edge of this signal and a conversion is initiated. The state of this pin at the end of conversion also determines whether the part is powered down or not. See operating modes section of this data sheet. 16 20 VDD Positive Supply Voltage 2.7 V to 5.5 V. PIN CONFIGURATIONS DIP/SOIC/TSSOP 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) AD7811 VREF DIN SCLK CONVST VDD CREF VIN1 AGND TFS RFS DOUT VIN2 VIN3 VIN4 A0 DGND 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) AD7812 VREF DIN SCLK VDD CREF VIN1 AGND TFS RFS DOUT VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 A0 DGND CONVST C |
Аналогичный номер детали - AD7812_15 |
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Аналогичное описание - AD7812_15 |
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