поискавой системы для электроныых деталей |
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CDP1823CD3 датащи(PDF) 4 Page - Intersil Corporation |
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CDP1823CD3 датащи(HTML) 4 Page - Intersil Corporation |
4 / 6 page 6-34 Access Time from MRD (Note 1) tAM 5 - 310 - 435 ns Data Hold Time After Read tDH 5 50 - 70 - ns NOTE: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing. Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF (Continued) PARAMETER SYMBOL VDD (V) LIMITS UNITS +25oC, -55oC +125oC MIN MAX MIN MAX ADDRESS tRC tAA tAM (NOTE 1) MRD tAC CS2, CS3, CS5 CS1, CS4 tDH HIGH IMPEDANCE VALID DATA 90% 10% NOTES: 1. Minimum timing for valid data output. Longer times will initiate an earlier but invalid output. 2. MWR is high during read operation. Timing measurement reference is 0.5VDD. FIGURE 1. READ CYCLE TIMING DIAGRAM (NOTE 1) Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF PARAMETER SYMBOL VDD (V) LIMITS UNITS +25oC, -55oC +125oC (NOTE 2) MIN MAX (NOTE 2) MIN MAX Write Cycle tWC 5 280 - 400 - ns Address Setup Time (Note 1) tAS 5 70 - 100 - ns Address Hold Time tAH 5 70 - 100 - ns Write Pulse Width (Note 1) tWW 5 140 - 200 - ns Data to MWR Setup Time (Note 1) tDS 5 70 - 100 - ns CDP1823C/3 |
Аналогичный номер детали - CDP1823CD3 |
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Аналогичное описание - CDP1823CD3 |
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