8

FIGURE 6. MODE 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES

FIGURE 7. OUTPUT PORT MODE 1 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION

SERVICE REQUEST TRUTH TABLE

CS1

or

CS2

CLOCK

or

CLEAR

SR/SR

1

SR/SR

0

DATA OUT

CLEAR

CS1

⋅ CS2

MODE 1 TRUTH TABLE

CLOCK

† CS1-CS2

CLEAR

DATA OUT EQUALS

0X

0

0

0

X

1

Data Latch

X

0

1

Data Latch

1

1

X

Data In

† CS1

NOTES

1. CS1

• CS2 is the overlap of CS1 = 0 and CS2 = 1.

2. Write is the overlap of CS1

• CS2 and CLOCK.

SR

DATA IN

CLOCK

(NOTE 1)

(NOTE 2)

CS2

CDP1852

DATA BUS

CS1

CLOCK

MODE

DATA IN

SR

DATA

DATA OUT TO

SIGNAL THAT INDICATES

DATA IS READY

CDP1802

MRD

MEMORY

ADDRESS

LINES

TPB

OUT

PERIPHERAL DEVICE

CDP1852 IS SELECTED

AND DATA IS

STROBED INTO IT’S

REGISTER WITH TPB

DATA IS OUTPUTTED

FROM THE CDP1852

AND THE PERIPHERAL

DEVICE IS SIGNALED

TPB

MRD

DATA BUS

DATA TO

SR/SR

VALID

DATA

PERIPHERAL

DEVICE

CDP1852, CDP1852C