поискавой системы для электроныых деталей |
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CDP1852CE датащи(PDF) 5 Page - Intersil Corporation |
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CDP1852CE датащи(HTML) 5 Page - Intersil Corporation |
5 / 9 page 5 Input Port Mode 0 - Typical Operation General Operation When the mode control is tied to VSS, the CDP1852 becomes an input port. In this mode, the peripheral device places data into the CDP1852 with a strobe pulse and the CDP1852 signals the microprocessor that data is ready to be transferred on the strobe’s trailing edge via the SR output line. The CDP1802 then issues an input instruction that enables the CDP1852 to place the information from the peripheral device on the data bus to be entered into a mem- ory location and the accumulator of the microprocessor. Detailed Operation (See Figure 5) The STROBE from the peripheral device places DATA into the 8-bit register of the CDP1852 when it goes high and latches the DATA on its trailing edge. The SR output is set low on the strobe’s trailing edge. This output is connected to a flag line of the CDP1802 microprocessor and software poll- ing will determine that the flag line has gone low and periph- eral data is ready to be transferred. The CDP1802 then issues an input instruction that places an NX line high. With the MRD line also high, the CDP1852 is selected and its out- put drivers place the DATA from the peripheral device on the DATA BUS. When the CDP1802 selected the CDP1852, it also selected and addressed the memory via one of the 16 internal address registers selected by an internal “X” regis- ter. The data from the CDP1852 is therefore entered into the memory [Bus → M(R(X))]. The data is also transferred to the D register (accumulator) in the microprocessor (Bus → D). When the CDP1802’s execute cycle is completed, the CDP1852 is deselected by the NX line returning low and its data output pins are three-stated. The SR output returns high. Minimum Data Setup Time tDS 5- -10 0 ns 10 - -5 0 ns Minimum Data Hold Time tDH 5 - 75 150 ns 10 - 35 75 ns Data Out Hold Time (Note 2) tDOH 5 30 185 370 ns 10 15 100 200 ns Propagation Delay Times, tPLH, tPHL Select to Data Out (Note 2) tSDO 5 30 185 370 ns 10 15 100 200 ns Clear to SR tRSR 5 - 170 340 ns 10 - 85 170 ns Clock to SR tCSR 5 - 110 220 ns 10 - 55 110 ns Select to SR tSSR 5 - 120 240 ns 10 - 60 120 ns NOTES: 1. Typical values are for TA = 25 oC and nominal V DD. 2. Minimum value is measured from CS2, maximum value is measured from CS1/CS1. Dynamic Electrical Specifications At TA = -40 oC to +85oC, V DD = ±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF, and 1 TTL Load (Continued) PARAMETER VDD (V) LIMITS UNITS MIN (NOTE 1) TYP MAX CDP1852, CDP1852C |
Аналогичный номер детали - CDP1852CE |
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Аналогичное описание - CDP1852CE |
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