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CDP1853D датащи(PDF) 1 Page - Intersil Corporation |
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CDP1853D датащи(HTML) 1 Page - Intersil Corporation |
1 / 6 page 4-35 CDP1853, CDP1853C N-Bit 1 of 8 Decoder Description The CDP1853 and CDP1853C are 1 of 8 decoders designed for use in general purpose microprocessor systems. These devices, which are functionally identical, are specifically designed for use as gated N-bit decoders and interface directly with the 1800-series microprocessors without additional compo- nents. The CDP1853 has a recommended operating voltage range of 4V to 10.5V, and the CDP1853C has a recommended operating voltage range of 4V to 6.5V. When CHIP ENABLE (CE) is high, the selected output will be true (high) from the trailing edge of CLOCK A (high-to-low tran- sition) to the trailing edge of CLOCK B (high-to-low transition). All outputs will be low when the device is not selected (CE = 0) and during conditions of CLOCK A and CLOCK B as shown in Figure 2. The CDP1853 inputs N0, N1, N2, CLOCK A, and CLOCK B are connected to an 1800-series microprocessor out- puts N0, N1, N2, TPA, and TPB respectively, when used to decode I/O commands as shown in Figure 5. The CHIP ENABLE (CE) input provides the capability for multiple levels of decoding as shown in Figure 6. The CDP1853 can also be used as a general 1 of 8 decoder for I/O and memory system applications as shown in Figure 4. The CDP1853 and CDP1853C are supplied in hermetic 16-lead dual-in-line ceramic (D suffix) and plastic (E suffix) packages. Features • Provides Direct Control of Up to 7 Input and 7 Output Devices • CHIP ENABLE (CE) Allows Easy Expansion for Multi- level I/O Systems Ordering Information PACKAGE TEMP. RANGE 5V 10V PKG. NO. PDIP -40oC to +85oC CDP1853CE CDP1853E E16.3 Burn-In CDP1853CEX - E16.3 SBDIP -40oC to +85oC CDP1853CD CDP1853D D16.3 Burn-In CDP1853CDX - D16.3 March 1997 File Number 1189.2 Pinout 16 LEAD DIP TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CLK A N0 N1 OUT 0 OUT 1 OUT 2 VSS OUT 3 VDD N2 CE OUT 4 OUT 5 OUT 6 OUT 7 CLK B CDP1853 Functional Diagram FIGURE 1. Qn 4 5 6 7 12 11 10 9 1 OF 8 DECODER OUT 0 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 2 3 14 N0 N1 N2 13 CE 1 15 CLOCK A CLOCK B (TPA) (TPB) EN TRUTH TABLE 1 = High level, 0 = Low level, X = Don’t care † Qn-1 = Enable remains in previous state. CE CL A CL B EN 1 0 0 Qn-1† 1011 1100 1111 0X X0 N2 N1 N0 EN 01234567 0001 10000000 0011 01000000 0101 00100000 0111 00010000 1001 00001000 1011 00000100 1101 00000010 1111 00000001 X X X 0 00000000 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 |
Аналогичный номер детали - CDP1853D |
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Аналогичное описание - CDP1853D |
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