AD9627_15 datasheet(11/76 Pages) AD

номер детали	AD9627

подробное описание детали	12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS

Download	76 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

Logo

11 / 76 page

AD9627

Rev. B | Page 11 of 76

SWITCHING SPECIFICATIONS—AD9627-80/AD9627-105

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and

DCS enabled, unless otherwise noted.

Table 6.

Parameter

Temperature

AD9627-80

AD9627-105

Unit

Min

Typ

Max

Min

Typ

Max

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

625

MHz

Conversion Rate

DCS Enabled1

Full

20

80

20

105

MSPS

DCS Disabled1

Full

10

80

10

105

MSPS

CLK Period—Divide-by-1 Mode (tCLK)

Full

12.5

9.5

ns

CLK Pulse Width High

Divide-by-1 Mode, DCS Enabled

Full

3.75

6.25

8.75

2.85

4.75

6.65

ns

Divide by-1-Mode, DCS Disabled

Full

5.63

6.25

6.88

4.28

4.75

5.23

ns

Divide-by-2 Mode, DCS Enabled

Full

1.6

ns

Divide-by-3 Through Divide-by-8

Modes, DCS Enabled

Full

0.8

ns

DATA OUTPUT PARAMETERS (DATA, FD)

CMOS Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD)2

Full

2.2

4.5

6.4

2.2

4.5

6.4

ns

DCO Propagation Delay (tDCO)

Full

3.8

5.0

6.8

3.8

5.0

6.8

ns

Setup Time (tS)

Full

6.25

5.25

ns

Hold Time (tH)

Full

5.75

4.25

ns

CMOS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

Full

2.4

5.2

6.9

2.4

5.2

6.9

ns

DCO Propagation Delay (tDCO)

Full

4.0

5.6

7.3

4.0

5.6

7.3

ns

Setup Time (tS)

Full

6.65

5.15

ns

Hold Time (tH)

Full

5.85

4.35

ns

LVDS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

Full

2.0

4.8

6.3

2.0

4.8

6.3

ns

DCO Propagation Delay (tDCO)

Full

5.2

7.3

9.0

5.2

7.3

9.0

ns

CMOS Mode Pipeline Delay (Latency)

Full

12

Cycles

LVDS Mode Pipeline Delay (Latency)

Channel A/Channel B

Full

12/12.5

Cycles

Aperture Delay (tA)

Full

1.0

ns

Aperture Uncertainty (Jitter, tJ)

Full

0.1

ps rms

Wake-Up Time3

Full

350

μs

OUT-OF-RANGE RECOVERY TIME

Full

2

Cycles

1 Conversion rate is the clock rate after the divider.

2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3 Wake-up time is dependent on the value of the decoupling capacitors.

Аналогичный номер детали - AD9627_15

производитель	номер детали	датащи	подробное описание детали
Analog Devices	AD9627-150EBZ	2Mb / 77P	1.8 V Dual Analog-to-Digital Converter

More results

Аналогичное описание - AD9627_15

производитель	номер детали	датащи	подробное описание детали
Analog Devices	AD9255BCPZRL7-80	1Mb / 44P	14-Bit, 125 MSPS/105 MSPS/80 MSPS REV. C
Analog Devices	AD9600ABCPZ-150	2Mb / 72P	10-Bit, 105 MSPS/125 MSPS/150 MSPS REV. B
NXP Semiconductors	ADC1213D	295Kb / 41P	Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 05-23 April 2010
Analog Devices	AD9253	1Mb / 40P	Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS REV. 0
	AD9627ABCPZ-125	2Mb / 76P	12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter REV. B
	AD9432BSQZ-80	517Kb / 16P	12-Bit, 80 MSPS/105 MSPS ADC Rev. E
	AD9432	517Kb / 16P	12-Bit, 80 MSPS/105 MSPS ADC Rev. F
	AD9432	441Kb / 17P	12-Bit, 80 MSPS/105 MSPS ADC
	AD9633	1Mb / 40P	Quad, 12-Bit, 80 MSPS/105 MSPS REV. 0
	AD9432	517Kb / 16P	12-Bit, 80 MSPS/105 MSPS ADC Rev. F

More results

AD9627 датащи(PDF) 11 Page - Analog Devices

AD9627 датащи(HTML) 11 Page - Analog Devices

Аналогичный номер детали - AD9627_15

Аналогичное описание - AD9627_15

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

датащи скачать

ссылки URL