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AD9895 датащи(PDF) 6 Page - Analog Devices |
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AD9895 датащи(HTML) 6 Page - Analog Devices |
6 / 58 page REV. A –6– AD9891/AD9895 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9891 and AD9895 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS With Respect Parameter To Min Max Unit AVDD1, AVDD2 AVSS –0.3 +3.9 V TCVDD TCVSS –0.3 +3.9 V HVDD HVSS –0.3 +5.5 V RGVDD RGVSS –0.3 +5.5 V DVDD DVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V RG Output RGVSS –0.3 RGVDD + 0.3 V H1–H4 Output HVSS –0.3 HVDD + 0.3 V Digital Outputs DVSS –0.3 DVDD + 0.3 V Digital Inputs DVSS –0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V VRT, VRB AVSS –0.3 AVDD + 0.3 V BYP1–BYP3, CCDIN AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature, 10 sec 350 °C ORDERING GUIDE Temperature Package Package Model Range Description Option AD9891KBC –20 °C to +85°C CSPBGA BC-64 AD9895KBC –20 °C to +85°C CSPBGA BC-64 PACKAGE THERMAL CHARACTERISTICS Thermal Resistance JA = 61 °C/W JC = 29.7 °C/W TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Unit MASTER CLOCK, CLI (Figure 7) CLI Clock Period, AD9891 tCONV 50 ns CLI High/Low Pulsewidth, AD9891 20 25 ns CLI Clock Period, AD9895 tCONV 33.3 ns CLI High/Low Pulsewidth, AD9895 13 16.7 ns Delay from CLI Rising Edge to Internal Pixel Position 0 tCLIDLY 6ns AFE CLAMP PULSES 1 (Figure 13) CLPDM Pulsewidth 410Pixels CLPOB Pulsewidth 2 220Pixels AFE SAMPLE LOCATION 1 (Figure 10) SHP Sample Edge to SHD Sample Edge, AD9891 tS1 20 25 ns SHP Sample Edge to SHD Sample Edge, AD9895 tS1 13 16.7 ns DATA OUTPUTS (Figure 12) Output Delay from DCLK Rising Edge 1 tOD 8ns Pipeline Delay from SHP/SHD Sampling 9 Cycles SERIAL INTERFACE (Figures 52 and 53) Maximum SCK Frequency fSCLK 10 MHz SL to SCK Setup Time tLS 10 ns SCK to SL Hold Time tLH 10 ns SDATA Valid to SCK Rising Edge Setup tDS 10 ns SCK Falling Edge to SDATA Valid Hold tDH 10 ns SCK Falling Edge to SDATA Valid Read tDV 10 ns NOTES 1Parameter is programmable. 2Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance. (CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 20 MHz [AD9891] or 30 MHz [AD9895], unless otherwise noted.) WARNING! ESD SENSITIVE DEVICE |
Аналогичный номер детали - AD9895_15 |
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Аналогичное описание - AD9895_15 |
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