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AD73460 датащи(PDF) 6 Page - Analog Devices |
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AD73460 датащи(HTML) 6 Page - Analog Devices |
6 / 32 page REV. A AD73460 –6– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73460 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS * (TA = 25 °C, unless otherwise noted.) AVDD, DVDD to GND . . . . . . . . . . . . . . . –0.3 V to +4.6 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40 °C to +85°C Storage Temperature Range . . . . . . . . . . . . –20 °C to +125°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150 °C PBGA, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 25°C/W Reflow Soldering Maximum Temperature . . . . . . . . . . . . . . . . . . . . . . 225 °C Time at Maximum Temperature . . . . . . . . . . . . . . . 15 sec *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Package Package Model Range Description Options AD73460BB-80 –40 °C to +85°C 119-Ball Plastic Grid Array B-119 AD73460BB-40 –40 °C to +85°C 119-Ball Plastic Grid Array B-119 TIMING CHARACTERISTICS–AFE SECTION* Limit at Parameter TA = –40 C to +85 C Unit Description Clock Signals See Figure 1 t1 61 ns min AMCLK Period t2 24.4 ns min AMCLK Width High t3 24.4 ns min AMCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period (SCLK = AMCLK) t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t 1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns max SDOFS Hold After SCLK High t11 10 ns max SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from AMCLK *For details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition. Specifications subject to change without notice. (AVDD = 3 V to 3.6 V; DVDD = 3 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted.) |
Аналогичный номер детали - AD73460_15 |
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Аналогичное описание - AD73460_15 |
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