ADE7754_15 datasheet(10/44 Pages) AD

номер детали	ADE7754

подробное описание детали	Polyphase Multifunction Energy Metering IC with Serial Port

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REV. 0

–10–

ADE7754

Figure 6 shows how the gain settings in PGA 1 (current channel)

and PGA 2 (voltage channel) are selected by various bits in the

gain register. The no-load threshold and sum of the absolute

value can also be selected in the gain register. See Table X.

0

7

6

5

4

3

2

1

0

RESERVED = 0

PGA 2 GAIN SELECT

00 =

1

01 =

2

10 =

4

PGA 1 GAIN SELECT

00 =

1

01 =

2

10 =

4

NO LOAD

ABS

GAIN REGISTER*

CURRENT AND VOLTAGE CHANNEL PGA CONTROL

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS

ADDR: 18h

Figure 6. Analog Gain Register

ANALOG-TO-DIGITAL CONVERSION

The ADE7754 carries out analog-to-digital conversion using

second order

Σ-∆ ADCs. The block diagram in Figure 7 shows a

first order (for simplicity)

Σ-∆ ADC. The converter is made up of

two parts, the

Σ-∆ modulator and the digital low-pass filter.

VREF

....10100101......

DIGITAL

LOW-PASS

FILTER

MCLK/12

INTEGRATOR

1-BIT DAC

R

C

ANALOG

LOW-PASS FILTER

1

24

LATCHED

COMPARATOR

+

–

Figure 7. First Order ( - ) ADC

A

Σ-∆ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7754, the sampling clock is equal to CLKIN/12.

The 1-bit DAC in the feedback loop is driven by the serial data

stream. The DAC output is subtracted from the input signal.

If the loop gain is high enough, the average value of the DAC

output (and therefore the bit stream) will approach that of the

input signal level. For any given input value in a single sampling

interval, the data from the 1-bit ADC is virtually meaningless. Only

when a large number of samples are averaged will a meaningful

result be obtained. This averaging is carried out in the second part

of the ADC, the digital low-pass filter. Averaging a large number of

bits from the modulator, the low-pass filter can produce 24-bit

data-words that are proportional to the input signal level.

The

Σ-∆ converter uses two techniques to achieve high resolu-

tion from what is essentially a 1-bit conversion technique. The

first is oversampling; the signal is sampled at a rate (frequency)

many times higher than the bandwidth of interest. For example,

the sampling rate in the ADE7754 is CLKIN/12 (833 kHz),

and the band of interest is 40 Hz to 2 kHz. Oversampling

spreads the quantization noise (noise due to sampling) over a

wider bandwidth. With the noise spread more thinly over a

wider bandwidth, the quantization noise in the band of interest

is lowered. See Figure 8.

Oversampling alone is not an efficient enough method to

improve the signal to noise ratio (SNR) in the band of interest.

For example, an oversampling ratio of 4 is required to increase

the SNR by only 6 dB (1 bit). To keep the oversampling ratio at

a reasonable level, the quantization noise can be shaped so that

most of the noise lies at the higher frequencies. In the

Σ-∆

modulator, the noise is shaped by the integrator, which has a

high-pass type of response for the quantization noise. The result

is that most of the noise is at the higher frequencies, where it

can be removed by the digital low-pass filter. This noise shaping

is shown in Figure 8.

FREQUENCY (kHz)

0

417

833

2

SAMPLING

FREQUENCY

SHAPED

NOISE

ANTIALIAS FILTER (RC)

DIGITAL FILTER

NOISE

SIGNAL

HIGH RESOLUTION

OUTPUT FROM DIGITAL

LPF

NOISE

SIGNAL

FREQUENCY (kHz)

0

417

833

2

Figure 8. Noise Reduction Due to Oversampling

and Noise Shaping in the Analog Modulator

Antialias Filter

Figure 7 shows an analog low-pass filter (RC) on the input to

the modulator. This filter is used to prevent aliasing, an artifact

of all sampled systems. Frequency components in the input

signal to the ADC that are higher than half the sampling rate of

the ADC appear in the sampled signal at a frequency below half

the sampling rate. Figure 9 illustrates the effect; frequency com-

ponents (arrows shown in black) above half the sampling

frequency (also known as the Nyquist frequency), i.e., 417 kHz,

get imaged or folded back down below 417 kHz (arrows shown

in gray). This happens with all ADCs, regardless of the archi-

tecture. In the example shown, only frequencies near the sampling

frequency, i.e., 833 kHz, will move into the band of interest for

metering, i.e., 40 Hz to 2 kHz. This allows use of a very simple

LPF (low-pass filter) to attenuate these high frequencies (near

900 kHz) and thus prevent distortion in the band of interest. A

simple RC filter (single pole) with a corner frequency of 10 kHz

produces an attenuation of approximately 40 dBs at 833 kHz.

See Figure 9. This is sufficient to eliminate the effects of aliasing.

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