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LF3330QC15 датащи(PDF) 10 Page - LOGIC Devices Incorporated |
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LF3330QC15 датащи(HTML) 10 Page - LOGIC Devices Incorporated |
10 / 15 page DEVICES INCORPORATED LF3330 Vertical Digital Image Filter 10 Video Imaging Products 11/08/2001–LDS.3330-M TABLE 14. LIMIT REGISTER LOADING FORMAT CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 1st Word - Address 1 1 1000000111 2nd Word - Data R R R R 01100000 3rd Word - Data R R R R 0* 0111011 4th Word - Data R R R R 10100100 5th Word - Data R R R R 0** 1110010 R = Reserved. Must be set to “0”. * This bit represents the MSB of the Lower Limit. ** This bit represents the MSB of the Upper Limit. TABLE 13. SELECT REGISTER LOADING FORMAT CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 1st Word - Address 0 1 1000000010 2nd Word - Data 0 0 0000001111 configuration register. Data value 003H is written into Configuration Register 2. Table 12 shows an example of loading data into a round register. Data value 7683F4A2H is written into round register 12. Table 13 shows an example of loading data into a select register. Data value 00FH is loaded into select register 2. Table 14 shows an example of loading data into limit register 7. Data value 3B60H is loaded as the lower limit and 72A4H is loaded as the upper limit. It takes 9S clock cycles to load S coefficient sets into the device. There- fore, it takes 2304 clock cycles to load all 256 coefficient sets. Assuming an 83 MHz clock rate, all 256 coefficient sets can be updated in less than 27.7 µs, which is well within vertical blanking time. It takes 5S clock cycles to load S round or limit registers. Therefore, it takes 160 clock cycles to update all round and limit registers. Assuming an 83 MHz clock rate, all round/limit registers can be updated in 1.92 µs. The coefficient banks and configura- tion/control registers are not loaded with data until all data values for the specified address are loaded into the LF InterfaceTM. In other words, the coefficient banks are not written to until all eight coefficients have been loaded into the LF InterfaceTM. A round register is not written to until all four data values are loaded. After the last data value is loaded, the interface will expect a new address value on the next clock cycle. After the next address value is loaded, data loading will begin again as previously discussed. As long as data is loaded into the interface, LD must remain LOW. After all desired coefficient banks and configuration/control registers are loaded with data, the LF InterfaceTM must be disabled. This is done by setting LD HIGH on the clock cycle after the clock cycle which latches the last data value. It is important that the LF InterfaceTM remain disabled when not loading data into it. |
Аналогичный номер детали - LF3330QC15 |
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Аналогичное описание - LF3330QC15 |
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