LF3347QC12 datasheet(4/10 Pages) LODEV

номер детали	LF3347QC12

подробное описание детали	High-Speed Image Filter with Coefficient RAM

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производитель	LODEV [LOGIC Devices Incorporated]

домашняя страница	http://www.logicdevices.com

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DEVICES INCORPORATED

LF3347

High-Speed Image Filter with Coefficient RAM

4

Video Imaging Products

08/16/2000–LDS.3347-G

FUNCTIONAL DESCRIPTION

Coefficient Banks

The LF3347 has four coefficient banks

which feed coefficient values to the

multipliers. Each bank can store 256

12-bit coefficients. In the example

shown in Table 3, address 10 in coeffi-

cient banks 1 through 4 is loaded with

the following values: ABCH, 789H,

456H, 123H. The coefficient banks are

not written to until all four coefficients

have been loaded into the device.

A7-0 determines which coefficient set is

sent to the multipliers. A value of 0 on

A7-0 selects set 0. A value of 1 selects

set 1 and so on.

Rounding/Offset

The accumulator output may be rounded

before being sent to the output select

section. Rounding is user-selectable and

is accomplished by adding the contents of

a round register to the accumulator

output (see Figure 2). There are sixteen

32-bit round registers. In the example in

Table 4, round register 10 is loaded with

76543210H. A round register is not

written to until all four data values have

been loaded into the device.

SELRND3-0 determines which round

register is used for rounding. A value of 0

on SELRND3-0 selects round register 0. A

value of 1 selects round register 1 and so

on. If rounding is not desired, a round

register should be loaded with 0 and

selected as the register for rounding.

Output Select

The filter output word width is 32-bits.

However, only 16-bits may be sent to the

device output. SHIFT4-0 determines

which 16 bits are passed to the device

output (See Table 1).

Output Limiting

An output limiting function is provided

for the output of the filter. When limiting is

enabled (LMTEN LOW), the limit register

selected with SELLMT3-0 determines the

valid range of output values for the overall

filter. There are sixteen 32-bit limit

registers. Each limit register contains both

an upper and lower limit value. The

lower limit is stored in bits 15-0 and the

upper limit is stored in bits 31-16. If the

value fed to the limiting circuitry is less

than the lower limit, the lower limit is

passed to the device output. If the value

fed to the limiting circuitry is greater than

the upper limit, the upper limit is passed

to the device output. When loading limit

values into the device, the upper limit must

TABLE 3.

COEFFICIENT BANK LOADING FORMAT

CC11CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0

1st Word

00

0

1

0

1

0

Address

2nd Word

10

1

0

1

0

Bank 1

3rd Word

01

11

1

0

1

0

1

Bank 2

4th Word

01

00

0

1

0

1

0

1

0

Bank 3

5th Word

00

01

0

1

0

1

Bank 4

TABLE 4.

ROUND REGISTER LOADING FORMAT

CC11CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0

1st Word

10

00

0

1

0

1

0

Address

2nd Word

RR

0

1

0

*0

3rd Word

RR

0

1

0

1

0

4th Word

RR

0

1

0

1

0

1

0

5th Word

RR

**0

1

0

1

0

TABLE 5.

LIMIT REGISTER LOADING FORMAT

CC11CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0

1st Word

11

00

0

1

Address

2nd Word

RR

0

1

0

1

3rd Word

RR

*0

0

1

4th Word

RR

1

0

1

0

1

5th Word

RR

**0

1

R = Reserved. Must be set to “0”.

* This bit represents the MSB of the Lower Limit Register.

** This bit represents the MSB of Upper Limit Register.

R = Reserved. Must be set to “0”.

* This bit represents the LSB of the Round Register.

** This bit represents the MSB of the Round Register.

be greater than the lower limit. In the

example shown in Table 4, limit register

15 is loaded with a lower limit of 0123H

and an upper limit of 7FEDH. A limit

register is not written to until all four data

values have been loaded into the device.

SELLMT3-0 determines which limit

register is used for limiting. A value of 0

on SELLMT3-0 selects limit register 0. A

value of 1 selects limit register 1 and so on.

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