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LF48908 датащи(PDF) 5 Page - LOGIC Devices Incorporated |
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LF48908 датащи(HTML) 5 Page - LOGIC Devices Incorporated |
5 / 16 page DEVICES INCORPORATED 5 LF48908 Two Dimensional Convolver 1 2 3 4 5 6 7 8 9 10 11 08/9/2000–LDS.48908-J Video Imaging Products Row Length Register The value stored in the Row Length Register determines the number of delay stages for each row buffer. The number of delay stages should be set equal to the row length of the input image. The Row Length Register may be loaded with the values 0 through 1023 (0 represents 1024 delay stages). It is possible to program the row buffers to have 1 or 2 delay stages, but this will lead to meaningless results for a 3 x 3 convolution. This register is loaded through CIN9-0 using the A2-0, CS, and LD controls. Once the Row Length Register has been loaded, a new value can not be loaded until the LF48908 has been reset. This is done by asserting RESET. After RESET goes HIGH, the Row Length Register must be loaded within 1024 CLK cycles. If the Row Length Register is not loaded within 1024 CLK cycles, the register will automatically be loaded with a “0”. Initialization Register The Initialization Register configures various functions of the device including: input data delay, input data format, coefficent data format, output rounding, cascade mode, and cascade input shift (see Table 3). This register is loaded through CIN8-0 using the A2-0, CS, and LD controls. Coefficient Registers - CREG0, CREG1 The Coefficient Registers are used to store the filter coefficients for the multiplier array. Each Coefficient through the CIN bus using A2-0, CS, and LD (see Figure 4). All the Control Logic Registers are set to their default values when RESET is active. FRAME does not affect the values in these registers. ALU Microcode Register Operation of the ALU and shifter are determined by the value stored in the ALU Microcode Register. This 10-bit instruction word is divided into two fields. The lower seven bits define the arithmetic and logical operations of the ALU. The upper three bits specify shift distance and direction. Tables 1 and 2 detail the various instruction words. This register is loaded through CIN9-0 using the A2-0, CS, and LD controls. Also see Arithmetic Logic Unit section. FIGURE 4. LF48908 CONTROL LOGIC BLOCK DIAGRAM A2-0 LD CS ADDRESS DECODE 3 ENCR1 ENCR0 CAS CR1 CR0 LMC EOR CIN9-0 10 ALU MICROCODE REGISTER LMC ALU MICROCODE 10 ROW LENGTH REGISTER EOR ROW LENGTH 10 INITIALIZATION REGISTER CAS INITIALIZATION DATA 9 8-0 I0 H0 G0 F0 E0 D0 C0 B0 A0 CR0 CR1 S R Q Q OE OE OE OE OE OE OE OE OE I1 H1 G1 F1 E1 D1 C1 B1 A1 OE OE OE OE OE OE OE OE OE ENCR1 ENCR0 I H G F E D C B A 8 8 8 8 8 8 8 8 8 COEFFICIENT REGISTER 0 COEFFICIENT REGISTER 1 9 7-0 8 7-0 8 |
Аналогичный номер детали - LF48908 |
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Аналогичное описание - LF48908 |
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