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8T73S1802 датащи(PDF) 2 Page - Integrated Device Technology |
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8T73S1802 датащи(HTML) 2 Page - Integrated Device Technology |
2 / 24 page 8T73S1802 DATA SHEET 1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER 2 REVISION 1 08/31/15 Block Diagram Pin Assignment 16-pin, 3mm x 3mm VFQFN Package 8XXXXXX EN SEL1 GND SEL0 8T73S1802 8 7 6 5 12 11 10 9 GND GND QB VCCO_QB 1 2 34 14 15 16 13 CLK nCLK QA nQA QB SEL0 SEL1 EN ÷1 ÷2 ÷4 ÷8 Control VBB Bias Generator VCC-1.3V Pullup Pullup Pullup Pin Description and Pin Characteristic Tables Table 1. Pin Assignment Pin Number Name Type1 Description 1VCC Power Power supply voltage for the device core and the inputs. 2CLK Input Non-inverting differential clock input. Compatible with LVPECL, LVDS and CML signals. 3 nCLK Input Inverting differential clock input. Compatible with LVPECL, LVDS and CML signals. 4VBB Output Bias voltage generator output. Use to bias the nCLK input in single-ended input applications. VBB = VCC - 1.3V. 5GND Power Ground supply voltage (GND) and ground return path. Connect to board GND (0V). 6GND Power Ground supply voltage (GND) and ground return path. Connect to board GND (0V). 7QB Output LVCMOS clock output QB. LVCMOS/LVTTL interface levels. If this pin is disabled by connecting its power supply pin VCCO_QB to GND, QB must be left open or connected to GND. 8VCCO_QB Power Positive supply voltage for the QB output. The QB output (if not connected) can be disabled by connecting this pin to GND. 9VCCO_QA Power Positive supply voltage for the QA, nQA output. The QA, nQA output (if not connected) can be disabled by connecting this pin to GND. 10 QA Output Differential clock output QA. LVPECL interface levels. If this pin is disabled by connecting its power supply pins VCCO_QA to GND, QA and nQA must be left open or connected to GND. 11 nQA Output Differential clock output QA. LVPECL interface levels. If this pin is disabled by connecting its power supply pins VCCO_QA to GND, QA and nQA must be left open or connected to GND. 12 VCCO_QA Power Positive supply voltage for the QA, nQA output. The QA, nQA output (if not connected) can be disabled by connecting this pin to GND. 13 SEL0 Input 60k Pullup Configuration pins. 3-Level interface. See Table 3 for function and Table 4D for interface levels. |
Аналогичный номер детали - 8T73S1802 |
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Аналогичное описание - 8T73S1802 |
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