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8V79S674 датащи(PDF) 10 Page - Integrated Device Technology

номер детали 8V79S674
подробное описание детали  Clock signal division and distribution
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производитель  IDT [Integrated Device Technology]
домашняя страница  http://www.idt.com
Logo IDT - Integrated Device Technology

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DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
10
REVISION 2 04/10/15
8V79S674 DATA SHEET
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Select Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k
 resistor
can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
2.5V LVPECL Input with Built-In 50Termination Interface
The IN /nIN with built-in 50
 terminations accept LVDS, LVPECL,
CML and other differential signals. Both VOH and VOL must meet the
VIN and VIH input requirements. Figures 1A to 1D show interface
examples for the IN/nIN with built-in 50
termination input driven by
the most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 1A. IN/nIN Input with Built-In 50

Driven by an LVDS Driver
Figure 1C. IN/nIN Input with Built-In 50

Driven by a CML Driver
Figure 1B. IN/nIN Input with Built-In 50

Driven by an LVPECL Driver
Figure 1D. IN/nIN Input with Built-In 50
 Driven by a
CML Driver with Built-In 50
 Pullup


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