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9ZXL0831 датащи(PDF) 8 Page - Integrated Device Technology |
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9ZXL0831 датащи(HTML) 8 Page - Integrated Device Technology |
8 / 18 page 9ZXL0831 8-OUTPUT LOW-POWER BUFFER FOR PCIE GEN1-2-3 AND QPI IDT® 8-OUTPUT LOW-POWER BUFFER FOR PCIE GEN1-2-3 AND QPI 8 9ZXL0831 REV C 070115 Electrical Characteristics–Skew and Differential Jitter Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES CLK_IN, DIF[x:0] tSPO_PLL Input-to-Output Skew in PLL mode nominal value @ 25°C, 3.3V -100 -60 100 ps 1,2,4,5,8 CLK_IN, DIF[x:0] tPD_BYP Input-to-Output Skew in Bypass mode nominal value @ 25°C, 3.3V 2.5 3.2 4.5 ns 1,2,3,5,8 CLK_IN, DIF[x:0] tDSPO_PLL Input-to-Output Skew Varation in PLL mode across voltage and temperature -50 50 ps 1,2,3,5,8 CLK_IN, DIF[x:0] tDSPO_BYP Input-to-Output Skew Varation in Bypass mode across voltage and temperature -250 250 ps 1,2,3,5,8 CLK_IN, DIF[x:0] tDTE Random Differential Tracking error beween two 9ZX devices in Hi BW Mode 15 ps (rms) 1,2,3,5,8 CLK_IN, DIF[x:0] tDSSTE Random Differential Spread Spectrum Tracking error beween two 9ZX devices in Hi BW Mode 5 75 ps 1,2,3,5,8 DIF{x:0] tSKEW_ALL Output-to-Output Skew across all outputs (Common to Bypass and PLL mode) 53 65 ps 1,2,3,8 PLL Jitter Peaking jpeak-hibw LOBW#_BYPASS_HIBW = 1 0 1.2 2.5 dB 7,8 PLL Jitter Peaking jpeak-lobw LOBW#_BYPASS_HIBW = 0 0 0.76 2 dB 7,8 PLL Bandwidth pllHIBW LOBW#_BYPASS_HIBW = 1 2 3 4 MHz 8,9 PLL Bandwidth pllLOBW LOBW#_BYPASS_HIBW = 0 0.7 1.1 1.4 MHz 8,9 Duty Cycle tDC Measured differentially, PLL Mode 45 50.1 55 % 1 Duty Cycle Distortion tDCD Measured differentially, Bypass Mode @100MHz -2 0 2 % 1,10 PLL mode 34 50 ps 1,11 Additive Jitter in Bypass Mode 17 50 ps 1,11 Notes for preceding table: 6.t is the period of the input clock 7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 8. Guaranteed by design and characterization, not 100% tested in production. 9 Measured at 3 db down or half power point. 10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 11 Measured from differential waveform Jitter, Cycle to cycle tjcyc-cyc 1 C L = 2pF with RS = 27Ω for Zo = 85Ω differential trace impedance. Input to output skew is measured at the first output edge following the corresponding input. 2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present. 3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4 This parameter is deterministic for a given device 5 Measured with scope averaging on to find mean value. |
Аналогичный номер детали - 9ZXL0831 |
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Аналогичное описание - 9ZXL0831 |
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