поискавой системы для электроныых деталей |
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UC1856-SP датащи(PDF) 9 Page - Texas Instruments |
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UC1856-SP датащи(HTML) 9 Page - Texas Instruments |
9 / 23 page Ip D2 L1 V O D1 Current Mode Control PWM I SENSE 8 V SENSE – V IN Q 1 Q 2 Np Np R S + N S N S I S C1 – + UC1856-SP www.ti.com SLUSBV6 – APRIL 2014 Feature Description (continued) The peak current mode control method is inherently unstable at duty ratios exceeding 0.5, resulting in sub- harmonic oscillation. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. A slope compensation must be added to the sensed current waveform or subtracted from the control voltage to ensure stability above a 50% duty cycle. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. The pulse width modulator (PWM) of UC1856-SP is limited to a maximum duty cycle of 50%, thus it can be used in topologies such as push-pull, half bridge, full bridge, forward, flyback configurations. Limiting PWM to 50% duty cycle ensures that for isolated or transformer based topologies. The transformer is allowed to reset and prevent saturation of the transformer core. Pulse-by-pulse symmetry correction (flux balancing) is inherent to current mode controllers and essential for the push-pull topology to prevent core saturation. Current limit control design has numerous advantages: 1. Current mode control provided peak switch current limiting – pulse by pulse current limit. 2. Control loop is simplified as one pole due to output inductor is pushed to higher frequency , thus a two pole system turns into two real poles. Thus system reduces to a first order system thus simplifies the control. 3. Multiple converter can be paralleled and allows equal current sharing amount the various converters. 4. Inherently provides for input voltage feed-forward as any perturbation in the input voltage will be reflected in the switch or inductor current. Since switch or inductor current is a direct control input, thus this perturbation is very rapidly corrected. 5. The error amplifier output (outer control loop) defines the level at which the primary current (inner loop) will regulate the pulse width, and output voltage. Figure 2. Push-Pull Converter Using Current Mode Control 8.3.1 Reference As highlighted in the Functional Block Diagram, UC1856-SP incorporates a 5.1-V internal reference regulator with ±10% set point variation over temperature. 8.3.2 Oscillator Figure 7 highlights the oscillator circuit. Connecting a resistor RT from pin 9 to ground establishes a current, which is mirrored to pin 8 and charges the capacitor connected from pin 8 to ground. Maximum on-time corresponds to the maximum charging time of the timing capacitor. Oscillator frequency can be determined by Equation 5. Off-time corresponds to capacitor discharge time establishes the converter dead time between the pulses according to Equation 4. Internal 8-mA current sink discharges the CT pin capacitor. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: UC1856-SP |
Аналогичный номер детали - UC1856-SP_15 |
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Аналогичное описание - UC1856-SP_15 |
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